MICROSOFT Aquires The Catholic Church
VATICAN CITY (AP) -- In a joint press conference in St. Peter's Square
this morning, MICROSOFT Corp. & the Vatican announced that the PC software
giant will acquire the Roman Catholic Church in exchange for an unspecified
number of shares of MICROSOFT common stock.
"We expect a lot of growth in the religious market in the next five to
ten years," said Gates, CEO of MICROSOFT. "The combined resources of
MICROSOFT and the Catholic Church will allow us to make religion easier
and more fun for a broader range of people."
Through the MICROSOFT Network, the company's new on-line service, "we
will make the sacraments available on-line for the first time" and revive
the popular pre-Counter-Reformation practice of selling indulgences," said
Gates. "You can get Communion, confess your sins, receive absolution
-- even reduce your time in Purgatory -- all without leaving your home."
( ESNUG 204 Item 1 ) ---------------------------------------------- [12/9/94]
From: Tom_Gourley@ccm2.hf.intel.com (Tom Gourley)
Subject: How To Better Navigate Through The SolvIt Maze
John,
I'm a relatively new Synopsys user (6 months) and I have tried using SolvIt
on several occasions to answer questions. While I'm able to extract lots of
information from SolvIt, some of which is quite interesting, I haven't had
much luck answering my specfic questions. I was just wondering are there
other users seeing this, too. What are people doing to get good results?
Perhaps my choice of seed-words could use some improvement.
- Tom Gourley
Intel
( ESNUG 204 Item 2 ) ---------------------------------------------- [12/9/94]
Subject: (ESNUG 203 #3) Model Tech & Synopsys VHDL Incompatibilities
> ... I had to develop several scripts in order to get Synopsys and ModelTech
> on the same wave length. One specific problem was the names of the generic
> delay values... Model Technology expects the generic to be "tsetup_d"
> instead of "tsuD".
From: kenychow@HK.Super.NET (Kenny Chow)
It's claimed that the VITAL standard is giving everybody the guideline of
all these names. The problem is one of whether or not the tool vendors (both
Synopsys and Model Tech) and the chip vendor (library provider) read and use
this standard.
- Kenny Chow,
Mentor Design Automation Ltd., Hong Kong.
( ESNUG 204 Item 3 ) ---------------------------------------------- [12/9/94]
Subject: (ESNUG 201 #6, 203#5) "Seeking User Wisdom On Floorplanning Tools"
> I'm trying to decide the best approach to floorplanning, and I've never
> used the Synopsys floorplanner, though I've used vendor floorplanning
> tools before.
>
> Can anyone comment on the relative merits of Synopsys floorplanner vs.
> vendor supplied floorplanners? Which is the better route for timing
> analysis (Synopsys or vendor)? Is a combined approach (both tools) best,
> or are they redundant or incompatible?
From: bobw@hlds.com (Bob Weiderhold)
Hi John,
A lot of people seem to be confused about the Synopsys Floorplan Manager
product. Seems like many people think its Synopsys' floorplanner.
Actually the name is quite misleading. It's not a floorplanner at all.
What the Synopsys Floorplan Manager provides is a set of specialized
optimization techniques which are not offered in the Design Compiler product.
When linked with actual floorplanning and/or placement & routing tools, it
can be a big help in solving timing problems-- especially with deep submicron
ICs. (I think the Synopsys Floorplan Manager probably got its name because
of the importance of its link to floorplanning and placement & routing tools
-- but I think many people find it pretty confusing.)
Basically the Synopsys Floorplan Manger allows you to backannotate both
physical clustering information (i.e. physical hierarchy) and more accurate
delay information from either a floorplanner or a placement & routing tool.
Then you can do full or incremental optimization using the backannotated info
using techniques like in-place-optimization (IPO) and critical path
resynthesis. The Synopsys Floorplan Manager also allows you to forward
annotate logic changes so floorplans can be updated incrementally. If you're
doing 0.5 micron designs of any size or speed I think people should probably
check the product out. If you're doing 0.8 micron designs that are large and
high speed it could also be a big help.
I was happy to hear the person from Hal Computer liked what he saw in our
(HLD Systems's) floorplanner product. Most customers like the fact that we
provide physical floorplanning capabilities as well as the ability to
accurately calculate delays based on the floorplan. The accurate delays can
be passed to Synopsys's Design Compiler & Floorplan Manager so timing
problems can be quickly identified and resolved.
- Bob Wiederhold
HLD Systems
( ESNUG 204 Item 4 ) ---------------------------------------------- [12/9/94]
From: mr@symbionics.co.uk (Martin Ryder)
Subject: I Want To Get & Keep Real MUXes -- Not Logical Equivalents!
John,
I've got a situation where an asynchronous external signal must be sampled.
The signal comes from an A-to-D converter with variable sampling clock.
There is no fixed relationship between the ADC clock and the logic clock,
except that there are many cycles of the logic clock between each sample.
The ADC clock can shift across a range of +/- one CLK period, in steps of a
small fraction of a CLK period.
The requirement is easily met: use a MUX to hold the old sample until the
new sample has settled (the actual requirement includes peak-following...see
the VHDL fragment below). Using a MUX to block the ADC input during
transitions also means there's no meta-stability risk.
___________________ ________________________ ____________
TC_DATA_IN ___________________X________________________X____________
_ _ _ _ _ _ _ _ _ _ _ _ _ _
CLK _| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_| |_
___ ___ ___
LOAD_PEAK _______| |__________________| |__________________| |_
(there are actually many more cycles of CLK between successive samples
than shown)
peak_reg : PROCESS (clk, tc_data_in)
VARIABLE abs_peak : signed(tc_data_in'RANGE);
BEGIN
abs_peak := abs( signed(tc_data_in) );
IF clk'EVENT AND (clk ='1') THEN
IF (peak_reset = '1') THEN
peak <= (OTHERS => '0');
ELSIF (load_peak = '1') THEN
IF (abs_peak > peak) THEN
peak <= abs_peak;
ELSE
peak <= peak;
END IF;
ELSE
peak <= peak;
END IF;
END IF;
END PROCESS peak_reg;
With v3.0c I get complex logic rather than MUXes: the synthesised circuit is
logically correct when all signals are static, but it does NOT block
TC_DATA_IN when (LOAD_PEAK = '0'). This puts transitions on the input of
the holding register whenever TC_DATA_IN changes (i.e. on every new sample.)
It's possible for this to happen close enough to the +ve edge of clk to
generate simulation violations, and also to create non-functioning silicon:
if bad data is sampled it screws up the rest of the system, it can't recover
even if it gets good data on the next cycle.
In v3.1b (same VHDL, same constraints, same library) I get MUXes, but the FAE
I contacted reckons this is down to slight differences in optimisation (i.e.
not a deliberate strategy to address this problem.) He has reproduced the
same structures I get, and has also created different structures from
slightly different releases of the same library! As a result I reckon my
safest option is to hand-place MUXes and then dont_touch them, but I'd like
a less clunky approach.....any suggestions?
- Martin Ryder
Symbionics Ltd
( ESNUG 204 Item 5 ) ---------------------------------------------- [12/9/94]
From: klein@ATB.teradyne.com (Larry Klein)
Subject: How Do I Get The "Synopsys Journal of High-Level Design" ???
In ESNUG 195 #4:
> This will do exactly what you want. (For more info see my paper "State
> machine design techniques for Verilog and VHDL" in the most recent issue
> of the Synopsys Journal of High-Level Design.)
Wow! There's a "Synopsys Journal of High-Level Design"? How do get it?
- Larry Klein
Teradyne
[ Editor's Note: The Journal is the new name for their old Methodology
Notes. Meth Notes changed name around August of this year. And, as with
the Meth Notes, the Journal's published every quarter. (You can get back
issues of Methodology Notes by calling 800-388-9125. Copies are $9.00 each
plus tax, and can be ordered using Visa, Mastercard, or American Express.)
Unlike the old Meth Notes, though, the Journal doesn't come via a
subscription. I'm told that the Synopsys FAEs are supposed to make sure
each customer receives a copy as they're published quarterly. (You
can also order additional copies of the Journal through the 800 number
for $9.00 per copy plus tax.)
If you're interested in contributing to the Journal, contact Ken Nelsen
at "knelsen@synopsys.com" and he'll set you up! - John ]
( ESNUG 204 Item 6 ) ---------------------------------------------- [12/9/94]
From: jonathan@ksr.com (Jonathan Frieden)
Subject: Seeking Best Verilog to FPGA Design Path
We're interested in putting together a Verilog -> FPGA development path. We
own Design Compiler Expert, Xact, Neocad. We've identified three plausible
paths, each with different costs and benefits and I'm interested in other's
experiences with this problem, so we can focus on the approaches most likely
to be successful.
Plan 1: Buy: Neocad's Synopsys FPGA compiler library &
Synopsys FPGA compiler
Design flow: Verilog + Neocad library -> FPGA compiler -> Neocad
Plan 2: Buy: Neocad's Synopsys DC Expert compiler library (status unclear)
Design flow: Verilog + Neocad library -> DC Expert -> Neocad
Plan 3: Buy: Exemplar
Design flow: Verilog -> Exemplar -> Xact (or Neocad)
I'm interested in finding if anyone has any experience with any of the
alternatives (or other reasonable alternatives) and how it went. Specific
issues would be: how well the synthesis, mapping, placement and routing work
in general and how well the design flow achieves the objective of converting
an HDL representation into a high speed design, making optimal use of the
physical resources of the part. Thanks for your help.
- Jonathan Frieden
Kendall Square Research
[ Editor's Note: Don't bother answering Jonathan directly. He sent me this
question and two days later KSR went belly up. I'm just publishing it
because I think it's a good question. - John Cooley ]
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