Editor's Note: Sorry about the 1 1/2 week delay of this latest issue of
ESNUG -- the system from where I do the e-mailings just got upgraded with
new hardware & new software. On top of this, USENET had/still has a
e-mail name recognition bug that's made life "interesting" to say the least.
Other hot news: my landlord just got two goats for the farm. I don't think
he knows how goats behave compared to sheep. Sheep usually spook at the
*slightest* provocation -- goats are only interested in what food one may
offer them, have no fear and just love to get into trouble! Egads!
- John Cooley
the ESNUG guy
( ESNUG 194 Item 1 ) ---------------------------------------------- [9/94]
Subject: (ESNUG 192 #6) "Creating SGE Schematics AFTER HDL Was Written"
> I want to: Create a SGE symbol from the existing VHDL/Verilog code
> - or -
> If I already create a symbol manually, how can I attach it to
> a corresponding existing Verilog/VHDL file?
---- ---- ----
From: stevem@asic.siecomp.com (Steve McChrystal)
We have used SGE to build top level schematics to bind various levels of
VHDL models together, and it works OK.
First, you have to create an SGE symbol for the VHDL entity, and manually
is the only way I've found. Carefully check the directions of the ports.
Save the symbol with the ENTITY name of the VHDL module it represents.
As you build your top levels of schematics, placing the symbol creates an
instance of the VHDL model. When this is converted to VHDL, there will be
an instance of the model in the code using the same name as the symbol.
Use of the same name along with the appropriate VHDL configuration create
the necessary binding.
When the VHDL is analyzed and elaborated, the module will be pulled from your
work library (or another if you've included the appropriate use statement)
and included in the simulation.
There are attributes you might want to set in the SGE environment for the
symbol and any schematic instances:
Symbol Attributes
VHDL_Cfg=configuration work.cfg_yourmodel Default Configuration
VHDL_Model=yourmodel suppresses component
statement for library
components
Schematic Instance Attributes
VHDL_Cfg overrides default configuration
Concerning SGE & Verilog in this case -- I'm familiar with Verilog and we
have the simulator; I don't have a license for the SGE to Verilog converter,
so I can't try it out.
I suspect that the situation is the same, that is the symbol which you
create is associated by name with the Verilog module. Obviously, you
don't have to worry about the entity-architecture association.
- Steve McChrystal
Siemens ICD Cupertino
[ Editor's Note: There's a hefty script users can get from Solv-It that was
too big to publish (14257 bytes, 532 lines) that can help you with this
"bug." Just e-mail to "solvit@synopsys.com" with a "get: QA-009223" along
with your user I.D. and it'll be automatically sent to you. - John ]
( ESNUG 194 Item 2 ) ---------------------------------------------- [9/94]
Subject: (ESNUG 193 #3) "Question for Verilog & VHDL Synthesis Buffs"
> While translating a piece of Verilog code into VHDL, I stumbled across
> the following variant of a "case" statement
>
> case ( 1'b1 ) // synopsys full_case parallel_case
>
> x[0] : temp = y[0];
> x[1] : temp = y[1];
> x[2] : temp = y[2];
>
> default : temp = 1'b0;
>
> endcase
>
> Synopsys interprets the comments parallel_case and generates mux type logic
> for this, evaluating all the expressions x[1]=='1' x[2]=='1' and x[0]=='1'
> in parallel. This generates a very fast design. However, I was unable to
> translate this case statement into equivalent VHDL code (any construct) that
> would give me the same sort of logic. Any ideas anyone?
[ Editor's Note: What follows is not the usual replies to the first
quoted item but a back-and-forth exchange on the topic. - John ]
-&&&- -&&&- -&&&-
jand@easics.be (Jan Decaluwe) opens with:
>The following VHDL code is equivalent. (This has been confirmed by
>Design Compiler's compare_design command.)
>
> case x is -- no // synopsys "cheating" required !
>
> when "000" => temp <= '0';
> when "001" => temp <= y(0);
> when "010" => temp <= y(1);
> when "100" => temp <= y(2);
> when others => temp <= '-'; -- explicit don't care in std_logic
>
> end case;
>
> - Jan Decaluwe
> Easics, BELGIUM
-&&&- -&&&- -&&&-
anand@lsil.com (Vijayanand Ponukumati) replies to Jan with:
>Jan: I guess what I was trying to imply was that given a template of the
>following nature in Verilog:
>
> case ( 1'b1 ) // synopsys full_case parallel_case
> expr1 : temp = val1;
> expr2 : temp = val2;
> expr3 : temp = val3;
> default : temp = 1'b0;
> endcase
>
>where expr1, expr2 and expr3 are any arbitrary expressions; there is no
>equivalent template in VHDL which would generate a parallel implementation
>and not a priority encoder.
>
>Your solution works for the example I originally mentioned, but not for the
>general template described above.
>
> - Vijayanand Ponukumati
> LSI Logic Corporation
-&&&- -&&&- -&&&-
jand@easics.be (Jan Decaluwe) concludes with:
Vijayanand: The generalization you require could be implemented as follows:
-- expr1, expr2, expr3 probably return booleans
-- `conv_active_high' converts an array of booleans into an
-- array of active high bits
...
variable Expr_123: three_bits;
...
Expr_123 := conv_active_high((expr1, expr2, expr3));
case Expr_123 is
when "000" => temp <= '0';
when "100" => temp <= val1;
when "010" => temp <= val2;
when "001" => temp <= val3;
when others => temp <= '-';
end case;
I do agree however that the Verilog template looks clearer because
an expression and the corresponding result are put on the same line.
The same could be done in VHDL by solving the problem in an alternative
way. The evaluations of the expressions are grouped in a vector Choice,
and possible results are grouped in a vector Result. The index of a
choice corresponds to the index of the corresponding result. Assignment
of choices and results can be organized so that the code is very
clear.
Then, a function is written that returns the index of the enabled choice.
Index 0 is included for the case none of choices is enabled, and another
index for the error condition in which more than one choice is enabled
simultaneously. (Index -1 would be appropriate, but as std_logic_vector
doesn't allow negative indices, I used `Choice'high + 1'). This
function is general and would normally be put in a package for re-use.
The final result is simply generated by indexing the result vector,
which is a non-prioritizing selection method.
One may argue that, as a result of VHDL's sequential semantics, the
priority encoder is now in the function. The essential difference is
that, in this case, the conditions are simple and logically exclusive;
a synthesis tool can be expected to take advantage of that.
The code would looks as follows:
architecture RTL of SELECTGEN2 is
function ReturnOneHotIndex (Choice: booleans) return integer is
variable Candidate: booleans(Choice'range);
begin
Candidate := (others => FALSE);
if (Choice = Candidate) then
return Choice'low-1;
end if;
for i in Choice'range loop
Candidate := (others => FALSE);
Candidate(i) := TRUE;
if (Choice = Candidate) then
return i;
end if;
end loop;
return Choice'high+1;
end ReturnOneHotIndex;
begin
-- expr1, expr2, expr3 are booleans here but could also be
-- boolean expressions without an essential difference
P: process (expr1, expr2, expr3, val1, val2, val3)
variable Result: std_logic_vector(0 to 4);
variable Choice: booleans(1 to 3);
begin
Result(0) := '0'; -- none of the choices true
Result(1) := val1; Choice(1) := expr1;
Result(2) := val2; Choice(2) := expr2;
Result(3) := val3; Choice(3) := expr3;
Result(4) := '-'; -- more than one choice true (error!)
temp <= Result(ReturnOneHotIndex(Choice));
end process P;
end RTL;
Unfortunately, I must admit that, unlike most of the times, the
synthesis tool (3.0c) disappointed me somewhat in that it was not able
to find the optimal solution with the default synthesis settings.
I had to turn flattening on (on the 1st compile !) and then it found
the optimal solution (confirmed by `compare_design').
- Jan Decaluwe
Easics, BELGIUM
( ESNUG 194 Item 3 ) ---------------------------------------------- [9/94]
From: stropparo@pasta.enet.dec.com (Peter A. Stropparo)
Subject: Hold Time Problems On A Single FF Breaks My Gate Array Size!
John,
When I use Design Compiler to fix hold times I run into a problem with
feedback loops. Synopsys adds the clock skew into the path to determine
how much hold time is needed. This is fine if the path starts and ends
at differant devices, but wrong when the path is a feedback path in a
statemachine, or on a MUXed flop.
The effect of using clock skew in the hold requirement for a path that
begins and ends on the same device in our case caused 6 extra un-needed
buffers to be added into the feedback loop of every flop. This adds 20%
to the final gate count of my design -- pushing it up to the next higher
size gate array! Any idea how to get around this bug?
- Peter A. Stropparo
Digital Equipment Corp.
( ESNUG 194 Item 4 ) ---------------------------------------------- [9/94]
From: uunet!fmicos!splinter!flieder (Jeff Flieder)
Subject: SNUG 1995 - Request for User Input
In a continuing effort to make the Synopsys Users Group as much of a user
conference as possible, the SNUG technical committee would like your input
for break-out session topics for next years conference. The following
sessions have been suggested by the committee, and we would like to know if
there are any other topics that users would like to see, or would like to
present.
- Layout Imact - Synthesis Strategies - ASIC Verification
- Designware - Library Compiler - Clock Tree Synthesis
- Logic Modeling Issues
If you have any other suggestions for session topics, please e-mail them
directly to me REAL SOON!. We will be sending out the call for papers soon
and would like to include as much user input as possible. Thanx.
- Jeff Flieder
SNUG '95 Technical Committee Chairman
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