( DAC 02 Item 5 ) ----------------------------------------------- [ 9/10/02 ]
Subject: Superlog, Vera, Verisity
DARWIN WAS RIGHT: In the Vera vs. Verisity battle, not much has changed
since I last reported on it 4 months ago in SNUG 02 #6. Other than the
specialized Verification Engineers, most everyday chip designers have little
or no interest in either Vera or Verisity's Specman "E". They'd rather
just stick to good olde Verilog or VHDL, thank you. (And rather than cut
and paste all their We-Don't-Care statements and place them here, I'll just
again refer you to SNUG 02 #6 here.) Vera vs. Verisity is one small market.
Dataquest FY 2000 Functional Test Simulator Market (in $ Millions)
Synopsys Vera #### $12.0 (43%)
Verisity Specman 'e' #### $12.0 (43%)
Forte/Chrono RAVE # $3.6 (13%)
Total ######### $28.0
The other repeat story here was how users liked Superlog's evolutionary
approach to improving Verilog. The responses here were all taken before
Synopsys bought Co-Design/Superlog. It's be interesting to see how users
react to the acquisition news.
"Superlog is different to E and Vera as it's not a testbench language
but a full HDL. Nice evolutionary path and it looks like it has some
great features. I like they way they've added abstractions, because
they've done many in a way hardware engineer can easily understand,
rather than some obscure software concept. "I can hide my data behind
an interface to my object widget mega-class? How does that help?"
versus "I can forget about my block interface and wrap it up in a
protocol? Nice." I exaggerate for effect, but you get the idea."
- Tom Fairbairn of 3Com Europe
"I think Superlog looks most promising. It adds to the Verilog syntax,
instead of replacing it."
- John Filion of Theseus
"Co-Design
Perhaps best-known for Superlog, CoDesign has been trying to sell a
tool that they say integrates the functions of multiple tools into
a single tool (with only one license). That tool contains all of the
following:
1) A Verilog simulator
2) An integrated C environment for verification
3) Advanced Verilog constructs for easier RTL writing
4) Advanced Verilog constructs for verification (replacing
Vera, E, or C++)
5) An assertion language (but not formal)
The good part is that this seems to make a lot of sense. They try to
provide a design and verification environment that will make engineers
feel comfortable (looks like Verilog), yet provides the constructs that
one finds in the verification languages. Their extensions have been
placed in the public domain, and have been accepted into the
Verilog2000 standard.
From a hardware designer viewpoint, some of the extensions seem nice.
Possibly the best one is the ability to group signals. This is an
attempt to cut down on the number of input/output declarations in
modules by declaring a bus and allowing modules to use the bus rather
than the pages of I/O. Synopsys has said it will support the
Verilog2000 standards. Until then, they have a tool that will
translate to Plain-Old-Verilog for synthesis.
The bad part is that you have to go and buy a new simulator, and use a
new verification tool. Most companies already own simulators, and the
existing simulators are very fast. While one could link Vera or E into
a Co-Design simulator, that would bypass the advantage of having a
single language for both the design and verification.
I have a hard time seeing how this Co-Design tool will be able to
compete with what is already out there. One could reasonably claim
that VCS already contains just about everything in Superlog."
- Andy Meyer of Zaiq Technologies
"I really like Superlog. It addresses most of the flaws in Verilog.
I've tested it and it rocks."
- Stefan Sandstrom of Axis
"Co-Design is doing a lot of PR for Superlog but ROI for Superlog
vs. Specman/Verilog doesn't compare. Less risk going to Specman
with an underlying Verilog simulator as well as less resistance,
while increasing the value of having a higher level of abstraction
to describe the test environment accurately."
- Jai Durgam of SiImage
"Vera baby, Vera. Vera+VCS+Linux == very fast sims.
Specman I used before, it's fine but was harder to get engineers who
knew the tool.
Superlog is cool, but not for verif yet. Give it time.
InnoLogic is very very cool but hard to implement in most flows. Needs
to integrate with Vera better (at all, actually)."
- [ An Anon Engineer ]
"My company uses VCS mostly but also maintains licenses for Cadence and
ModelSim simulators. Over the past year, the verification team has
started using Vera. Vera has been a great help for writing thorough
tests quickly, but I don't like that it ties us in to a Synopsys-only
flow. I would be more comfortable with Vera if it were well supported
by one or more major Synopsys competitors."
- Jonah Probell of Lexra
"e language/VERA: I just know e a little bit and though you have
a high learning curve it really pays back afterwards. The problem
is not the language itself - for a VHDL/Verilog designer you have
to understand the concept of the language. If you use it in the
same way as your HDL than e is very inefficient and you will
struggle more than you gain. Former SW designers often write better
e coder than HW designers."
- Raimund Soenning of Philips
"Verisity's 'e' remains the most powerful and flexible language for
doing verification. The trend of Verisity innovating and Synopsys
copying their features continues. Futures demos by both companies
drive home this point. If imitation is indeed the sincerest form on
flattery then Verisity should be thrilled because everyone is copying
what they pioneered."
- Sean W. Smith of Cisco Systems
"Verisity's E is a difficult language, and Vera should have been more
like Verilog. The donation of Vera-lite to Accellera's SystemVerilog
may succeed in adding the needed testbench facilities to Verilog. In
the end, though, I think people will just use C. This gives Superlog
an edge, since they have an efficient C interface. VCS is also doing
the right thing here."
- John Sanguinetti of Forte Design Automation
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