( SNUG 02 Item 6 ) --------------------------------------------- [ 5/15/02 ]
Subject: Verisity Specman 'e', Synopsys Vera, Chronology/Forte RAVE
STRUGGLING FOR MINDSHARE: When I asked about Vera/Specman/RAVE usage, the
most common response I received was 'we don't use them' and 'we make our own
test suites with C/Perl/Verilog' -- which means it's one small market.
Dataquest FY 2000 Functional Test Simulator Market (in $ Millions)
Synopsys Vera #### $12.0 (43%)
Verisity Specman 'e' #### $12.0 (43%)
Forte/Chrono RAVE # $3.6 (13%)
Total ######### $28.0
Functional verification is supposedly one of the biggest bottlenecks in chip
design these days, yet so far EDA companies can't seem to make any serious
cash selling in this niche. $28 million is chump change for a *serious*
design problem. The year before it was $22.4 million. Chump change.
"The funny thing is Vera and 'e' sell to different markets. Vera sells
to the design teams. 'e' sells to the verification teams."
- Gary Smith of Dataquest
"Three new languages? No thanks. But I think the real question here
is how did these guys come up with their product naming??? It seems
to me that around the bay area, 'RAVE' and 'e' are two things that
you more commonly find in the clubs on weekends in the San Francisco
SOMA district then something you use to verify chips."
- Jeff Waite of Netergy Microelectronics
"I prefer Perl test benches. I generate input vectors in Perl and
compare output vectors with Perl. I don't really want to learn yet
another language."
- Kevin Hubbard of Siemens
"Although Specman/E and Vera are roughly equivalent in features, I get
the feeling that Specman is in the lead. I'll bet both will be dead
when System Verilog has all those features. Vera and Specman basically
highlight weaknesses in the HDL for verification, and it looks like
that's exactly where System Verilog is headed."
- James Lee of Intrinsix
"Why use Vera/e/RAVE? C/C++ is the way to go. You can do anything you
like and C/C++ doesn't handcuff you like those 3 do."
- Scott Vincelette of Flarion
"e: I love its macros. I can add just about any construct I want to.
It's like a back door into the language. I hate all those curly
brackets and semi-colons. (Also, add good debug environment,
will ya?)
Vera: I love the stream generator. Someone did their homework on
this one. Please, please, please let me add constraints
standalone, and while you're at it grow the constraint language
(and the conflict checking).
Having worked in both 'e' and Vera for several years now, I typically
like the one I am not currently using at the time."
- Peet James of Qualis
"Don't use either. Can't get excited about learning 'e'. (Have you
seen the manual?)"
- Brent Lawson of Texas Instruments
"I don't use any of these. I typically use VHDL under ModelSim for
testbenchs."
- Donald Whisnant of John Deere
"The majority of my customers are using Verisity Specman. Personally.
I'm agnostic."
- Tom Moxon of Moxon Design
"I'm in the same boat as Gregg Lahti. These new verification languages
are all nice and dandy, but I haven't seen anything they do that can't
be done with standard tools (Perl/shell/C) to justify their cost."
- Doug Hillmer of XTAR
"We are using our internal test generator and analyzer. Using Specman
in our case required much more human resources and do not have any
advantage over our own in-house tool."
- Gideon Paul of TeraChip
"We use 'e' here, although I have used Vera before. If you are
devloping complex code I think the Specman debugging environment
is much better."
- Shirish Gadre of Sony
"These appear to be dead-end languages. Of these Vera is 'open' though
I know of only one vendor selling the tool. So all of these suffer
from the same proprietary language issues."
- an anon engineer
"Vera's what we use."
- Tom Heynemann of Compaq
"Synopsys tries to convince me of Vera with the argument of its strict
object orientation. Otherwise I (or somebody else) might corrupt data
within the deeper layers of my sources from the top. But that is
exactly what I want and this is possible with the aspect-orientated
approach of Specman and e.
Synopsys still tells the users how difficult it is to pick up e. At
the same time they refer to a bulky Vera-training book making it much
easier to pick up Vera -- why should this be necessary? And when I
have to decide between a book and substantial onsite e support where
I don't get lots of answers to questions I never asked it is rather
clear what I prefer."
- Andreas Dieckmann of Siemens
"Verisity is clearly emerging as the leader over Vera for functional
verification tools. The Specman Elite tools are easier to use, and
the growing list of third party eVC (e Verification Components)
provide a clear path toward a modular plug & play approach to building
test benches. Verisity is constantly improving their tools in order
to make verification easier. I can't wait to see what Verisity comes
up with next."
- Steven Besser of Intrinsix
"I can't really compare because I haven't tried Vera or Forte. I
attended a Specman training recently and found it easy to understand
once the concepts underlying its design were described. I like the
constraint solver and the concept of temporal expressions (just
like regular expressions, temporal expressions allow an infinite
sequence to be described using finite number of operators). There
is a learning curve associated with the e Language, but that is
true for any HVL.
The only point of comparison I have is with Cadence TestBuilder which
is basically a C++ library for verification. The biggest hurdle was
that C++ does not have language support for concurrency and garbage
collection. Therefore writing a verification environment is like doing
a C++ project. It takes a long time before there is any meaningful
testcase. There is also no debug environment for the tests. For
example, if there is a failure, it is hard to find out why. Specman on
the other hand, has GC and other features desirous of any HVL and
therefore we like it very much."
- an anon engineer
"I did not heard about RAVE before. We are using Specman and satisfy
with its verification approaches."
- Hui Fu of Infineon
"We are *very* happy with Specman. It is an orders of magnitude
improvement over our previous Verilog-only verification environment.
We last evaluated Vera a couple of years ago, but went with Specman
instead."
- Mark Gonzales of IBM
"Vera and Specman are getting the most press. I have not heard of RAVE.
We are not using any of these tools so I don't have a feel for this."
- an anon engineer
"We have talked to the sales reps but haven't selected any such tool.
Vera and e appear to be the popular choices with Vera being easier
to learn and utilize while e is more powerful. Therefore we would
probably go with Vera since we don't need the horsepower (or the
complexity) associated with e."
- Scott Campbell of Motorola
"These tools (Vera/Verisity-Specman/Forte) force a split between design
and verification. With all the languages an engineer needs to know,
adding another one does not solve any problems. Most, if not all
projects I have ever worked on re-use designer to help out with
verification. When using these new language it becomes nearly
impossible to share engineering resources. "
- Neel Das of Corrent Corp.
"We will be looking at Vera in the next 6 months."
- an anon engineer
"We use Specman partly because a partner was using it. My sense is that
Verisity is winning because their technology is good enough and they
market/partner very well. That enabled us to be creative for co-
verification. This was one case where we overrode the 'short vendor
list' approach."
- Curt Beckmann of Rhapsody Networks
"Forte's Rave is dead. Nobody bought it. Vera and Specman are still
too close to call, but I'm betting on Vera, for a variety of reasons.
The open-thing for one, and the fact that it's part of Synopsys, for
another."
- Dave Chapman of Gold Mountain
"Actually, I'm more interested in Forte's Perspective tool. We have
been asking ourselves whether there's a better way to answer the
question:
- did the test we wrote or the stimulus we generated actually
*cover* the intended specification item? i.e., did we really
test what we were supposed to test?
It seems like Forte Perspective might be a way to answer that question.
Someone, of course, would have the job of translating the design
specification document into the Perspective language, but once you
do that, Forte's tool could help you keep track of your functional
coverage.
Some of this is covered by elements of Specman and Vera, but I haven't
seen anyone coming from the direction Perspective takes.
We haven't used it yet, but we're planning to set up an evaluation."
- Kris Monsen of Mobilygen Corp.
"We don't use these."
- an anon engineer
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