( BSNUG 00 Item 5 ) ------------------------------------------- [ 10/13/00 ]
Subject: Veritools, Tensilica, Synopsys LM Models, Silicon Perspectives
THE REST OF THE WORLD: One of the nice things about SNUG gatherings is that
rival, non-Synopsys EDA vendors are given a night to push their wares, too.
Sometimes a delicate issue, it's good to see hot competitors like Verisity,
Monterey, and C-Level giving their pitches at the Boston SNUG -- them being
allowed into the Synopsys tent insures that SNUGs are *user* driven instead
of Synopsys marketing driven. (And it appears that Silicon Perspectives is
still missing those 16 tape-outs they claimed to have at DAC this year...)
"During the Vendor Fair I let some of the marketing/sales weenies talk
my ear off. These were the highlights:
- Undertow suite looked *really* cool! We looked at Veritools'
Verilog linter, but never looked at the tools suite that included
it, Undertow. The tool essentially is a waveform viewer that
incorporates the source code into the equation. This allows the
designer to for instance, click on a waveform event and be shown
were in the RTL code that event occured. It also infers state
machine diagrams from RTL, provides schematic views (like Design
Analyzer from Synopsys, but seemed more powerful, linked the
originating code and allows tracing of simulation values), allows
for searching the sim database for complex event occurances similar
to a logic analyzer, it can compare two simulations and display the
differences. The tool also offers true single step trace
capability to simulations similar to what the software guys offer
our customers via our emulation suites. I definitely think we
should get this tool in and evaluate it.
- Synopsys LM models group has a lot of stuff to pick from when
developing a system testbench. Also capability to setup a
hardware/software co-simulation/validation testbench. This might
be of use in letting software/apps get a head start developing
compilers, application code, etc.
- Tensilica just released a customizable, synthesizable processor with
a DSP co-processor option for use in system-on-chip designs. Really
neat stuff, you customize it via GUI interface! Just select your
data path size 8-,16-,or 24-bit, data width, and memory bus widths,
push a button and it plunks down a parameterized uprocessor/DSP
core. Pricey @ $150K.
Had no time for anything more."
- Brian Fall of Microchip Technology, Inc.
"John,
We had a visit from our friendly Silicon Perspective sales team today
and the demo they showed sparked some interest. They claimed to have
several tape-outs under their belt at this point, which is when I
thought, "Yeah, but have you told Cooley about them yet?". Heard any
more from the masses on this one? Their "don't flatten the hierarchy"
approach to floor planning certainly has some major benefits. Just
thought I'd look for some further references before engaging in any
kind of benchmark."
- Pete Churchill of Conexant Systems
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