( DAC 00 Item 34 ) --------------------------------------------- [ 7/13/00 ]
Subject: Silicon Perspectives 'First Encounter'
MORE SMOKE & MIRRORS: In the battle for tape-outs, one physical synthesis
start-up came out of nowhere claiming to have a whopping 16 customers tape-
outs at DAC! That company was Silicon Perspectives. Their tool, "First
Encounter" is yet another placement optimizer that's sandwitched between
post-Synopsys synthesis and right before your Avanti or Cadence detailed P&R
(just like Mentor's TeraPlace and Avanti's Saturn.) First Encounter's
supposed claim to fame is speed in doing what it does and those 16 customer
tape-outs. Their tool doesn't logically restructure gates but just does
buffer and cell resizing plus transition time fixing. It doesn't do legal
routing, so its output is a Verilog netlist plus the LEF/DEF/TDF/TF files
required to enable you to do your own Avanti/Cadence legal routing. It
supposedly can write out Synopsys DC constraints for re-synthesizing and
PrimeTime timing verification.
The gotcha I found with Silicon Perspectives was those supposed 16 customer
tape-outs. They were very evasive about them, wouldn't name names, but
gave details of each tape-out and later mentioned customer names. Playing
that little game where you see "S3" and "100 Mhz graphics chip" and YOU'RE
ASSUMING that it was S3's 100 Mhz graphics chip. It's a fun game until
you actually do some snooping to test your conclusions and discover that it
was Trident (who is going out of business) that did the graphics chip. I
can confirm that AMD used Silicon Perspectives somehow because Goering got
the story on http://www.EEDesign.com a few weeks ago. When I snooped into
Kawasaki Steel, I found they supposedly taped out a Silicon Perspectives
design but they also used Gambit, some PKS, some WarpRoute, DC, and weren't
too sure how much actual First Encounter useage they actually used. The
more I looked, the more used I felt in even giving them the initial benefit
of the doubt for their tape-out claims. I think they should either directly
name names with specific tape-outs or shut the fuck up. It's insulting to
be jerked around like this.
"* Silicon Perspectives: The demo was really impressive. They have an
incredibly lightweight and fast run-time data model. This enables
them to handle extremely large designs. They have a floorplanner
which can potentially create the best block pin assignments possible.
They do this by flattening the hierarchy, and doing a quick placement
on the flat netlist with region constraints. This is followed by
global routing, which creates a pin assignment on the blocks. They
ran the placement live on a netlist with 650K nets and 600K cells.
Took about 20 minutes! Although their pin-assignment strategy
provides the best optimization, it simply pushes out the need for pure
hierarchical design features, rather than eliminating their need."
- an anon engineer
"Still like Silicon Perspective. It works on real silicon problems.
Think they will be around since they are actually being used to produce
designs. Of course Synopsys's Physical Compiler looks great. We have
to see it working rather than being demoed. Monterey looked interesting
also, but not as much as Synopsys. (Magma and the rest sound
unbelievable, maybe they are...)"
- an anon engineer
"-PhysOpt: it's good to let the DC find out about its own crappy
constraints
-Magma: seems to be doing good, because it supports all
timing-closure-desperates with at least a DIFFERENT idea
-Silicon Perspective: looks incredibly fast
General: I believe, that the efforts to identify layout feasibility at
RTL design are a good idea. However, it will only work out, if the
required knowledge about backend issues (DSM, routability measures)
can be limited."
- an anon engineer
"We have been big believers for some time on using placement early in the
flow to help converge on timing quicker. In fact we had some in house
custom tools to help us do just that, without however a wide range of
IPO capability. The first ones on the scene that we took a look at
earlier last year were Sapphire, Silicon Perspectives, and Magma. We
placed our money on Silicon Perspectives primarily because they appeared
to be the furthest along and they would fit fairly easily into our
current flow. Have used them in-house for ~6 months in production. 1st
chip came back from fab early 5/2000. Met our timing goals (actually
exceeded a bit) and verified functionality correct.
I would say overall we have been more than satisfied with results we
have gotten from the tool to date. Attributes we appreciated the most:
o experts available to come on-site to help us through critical issues
o stability/maturity of tool better than expected (Yes there were bugs
but it delivered on all the functionality that was promised and some
of this functionality was just this side of Beta). I should add
here that when bugs were found, they were addressed very quickly.
o IPO worked well.
o accuracy of estimated timing out of Silicon Perspectives vs.
'sign-off' (extracted) timing was excellent (+/- 4%)
To me the next step in the evolution of these types of products is
coupling with the actual synthesis algorithms. The folks that I have
seen that have the advantage here are Synopsys/Cadence/Magma. We have
taken our most recent look at PhysOpt and it looks real."
- an anon engineer
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