( ESNUG 580 Item 4 ) ---------------------------------------------- [03/16/18]
Subject: Cooley's 11 questions about this Cadence/Imec first 3nm tapeout
TELL ME MORE: About two weeks ago, Cadence and Imec put out a happy-happy,
joy-joy press release claiming
Imec and Cadence tape-out industry's first 3nm test chip
which was very light on the many technical details that a chip designer
or chip verification guy would want to know. I chased these details
down before when CDNS and Imec did their "industry's first 5nm tapeout".
The untold parts of that IMEC "world's first 5nm tapeout" story
But since I'm currently caught up in a chip contract right now, I don't
have the cycles free to cut through all the B.S. involved with teasing out
this info for this alledged "industry's first 3nm tape-out".
Instead, here's what I would chase down if I had the time ...
1.) What are the general specs of the 3nm Imec chip? How many
instances? What clocks? What percent memories? Why type
of memories?
2.) When is their first 3nm silicon? Is Imec fabbing it? TSMC?
3.) Is this "common industry 64-bit CPU" an ARM core chip? Or
an Imagination core? Or a RISC-V core? Who's std cell lib
did you use?
4.) How did they verify the chip? UVM? SystemVerilog? Specman?
5.) What emulators did Imec use? Palladium? Veloce? Zebu?
6.) Who's DRC/LVS flow did Imec use? Calibre? Pegasus? PVS?
How many violations at the beginning? How many at the end?
Why was there no mention of Cadence Pegasus DRC in the
Imec 3nm press release? How many design rules in a 9T 3nm
deck?
7.) Did Imec use a 100% Cadence Innovus PnR flow? Or was Synopsys
ICC2 involved in any way as a back-up? Or on some blocks?
8.) Did Imec use a 100% Cadence Genus RTL synthesis flow? Or was
Synopsys Design Compiler used in any way?
9.) Did Imec use a 100% Cadence Tempus STA flow? Or was Synopsys
PrimeTime used in any way? How well did Tempus correlate with
PrimeTime? Did the Imec guys try any timing ECOs with Tempus
on this 3nm chip? What was used for final sign-off?
10.) Did Imec use a 100% Cadence Voltus IR-drop flow? Or was Ansys
Redhawk / Gear / SeaHawk / SeaScape used in any way? Why was
there no mention of Cadence Voltus IR-drop in the 3nm Imec
tapeout press release? What was used for final sign-off?
11.) Did Imec use a 100% Cadence Quantus QRC extraction flow? Or
was Synopsys Star-RC or Mentor Calibre xACT used in any way?
What was used for final sign-off?
IMPORTANT: If you have the answers to any of these questions, please email
them to me -- and, yes, you and your company will be 100% ANONYMOUS.
I don't care if they're "official" answers or not. I'm just curious about
the details here and I just don't have the time to chase them. Thanks.
- John Cooley
DeepChip.com Holliston, MA
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