( ESNUG 510 Item 1 ) -------------------------------------------- [12/21/12]
Subject: Murph tips details of the new Cadence-ARM-Samsung 14 nm tape-out
> ARM and Cadence Design Systems, Inc. today announced the tape-out of the
> first 14-nanometer test chip implementation of the high-performance ARM
> Cortex-A7 processor, the most energy-efficient processor from ARM.
From: [ John "Murph" Murphy of Cadence ]
Hi, John,
Yesterday Cadence, ARM, and Samsung jointly announced a new 14 nm tape-out.
I thought I'd follow up with the details for your readers.
This test chip was a joint 8 week project code named "Bluefin" completed in
September. It's already now in manufacture at Samsung.
Because it was only 8 weeks long, Project Bluefin's goal was NOT to do a
power/performance/area (PPA) optimization, but instead to test and debug how
to tape-out a chip using complex low power 32-bit ARM cores plus Artisan std
cell libs, memories, and I/O's inside a Cadence RTL-to-sign-off flow in the
Samsung 14 nm FinFET process.
We chose the ARM Cortex-A7 processor because of the high likelihood it
would be designed into smartphones, tablets, and other mobile devices.
We chose Samsung 14 nm bulk CMOS FinFETs because it's one of the major low
power processes engineers would design to.
Our goal was to have Cadence-ARM-Samsung hand-offs fully debugged.
TOOLS & LIBRARIES
For this project, ARM developed the foundation IP libraries for 14 nm
using Virtuoso 6.1.5 and 12.1 for LEF out -- which can do colorized,
double patterned custom design. These libs were then abstracted and
used in a digital RTL Compiler 11.1, Encounter Digital 11.1 & 12.1,
Encounter Test 11.1, Cadence QRC 11.1, Cadence ETS 11.1, and Cadence
EPS 11.1 flow.
DOUBLE PATTERNING HAS CHANGED
Our new way of handing-off has to do with when the metal layer assignment
is done and the effect it has on timing pessimism.
Before Project Bluefin, double patterned designs were handed-off to the
foundry as if there was only ONE mask for the double patterned metal
layers. (The foundry would then perform layer assignment as part of the
decomposition process for mask prep. This lack of colorization adds
uncertainty to the timing model, which the fabs guardband against.)
On the Bluefin project, we did the layer assignment inside our Encounter
Digital, which we then handed off to the foundry and preserved through
mask prep. (With the layer assignment info available in layout, or
"colorized", the metal traces are assigned to a given mask and identified
by a color which makes the assignment distinct. This lets a designer see
the different masks when the layout is visualized.) Then, because Cadence
RC extraction has been rewritten to recognize colors, the timing model
uncertainty is reduced -- thus no need for fab guardbanding!
By using Encounter Digital with this reduced timing pessimism, a designer
can be more aggressive to extract more Mhz from his or her 14 nm FinFETs.
No other EDA company has done a colorized hand-off that was preserved
through to manufacturing. Only Cadence has this advantage.
---- ---- ---- ---- ---- ---- ----
Also, our choosing NOT to obsess with PPA optimization for this first test
chip let our project engineers spend more time checking out that all the
new Samsung 14 nm FinFET design rules were being accurately obeyed in the
Cadence flow. (Although FinFETs use less power, their 3D nature means
more complex design rules plus new resistance and capacitance parasitics
that must be extracted and modeled.)
It was a full Cadence RTL-to-signoff flow with a very tight schedule.
I wish to thank the engineers on Project Bluefin from Samsung (Giheung,
Korea) to ARM (Cambridge & Sheffield, UK; San Jose, CA; Hsinchu, Taiwan)
and Cadence (Cambridge & Bracknell, UK; Munich, Germany; Austin, TX and
San Jose, CA) for making this tape-out successful.
- John "Murph" Murphy
Cadence Design Systems San Jose, CA
---- ---- ---- ---- ---- ---- ----
Editor's Note: This is Cadence's second 14 nm tape-out; they did
an ARM M0 core in an IBM SOI process. See ESNUG 514 #1. - John
---- ---- ---- ---- ---- ---- ----
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