( ESNUG 572 Item 6 ) -------------------------------------------- [06/06/17]

Subject: Jason Xing unhappy his ICScape ALPS SPICE was forgotten last year

  NEW! -- Silvaco SmartSpice Pro is Iliya's new push into the memory
  fastSPICE market.  Claims "true SPICE behavior but with much faster
  generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
  designs with better waveform overlay results than other simulators."
  Does 28/16/14/10nm.  SmartSpice (golden), SmartSpice HPP (parallel).
  (booth 649)  Ask for Colin Shaw.  Freebie: tin cups & golf balls

  CDNS Spectre-XPS is Lip-bu's comeback FastSPICE tool for memories.
  Benchmarked 3-4X faster throughput than SNPS HSPICE in ESNUG 547 #3.
  Has clever fast-or-accurate partitioning based on need.  Multi-core.
  (booth 107)  Ask for Wilbur Luo.  Freebie: Denali party tickets

  ProPlus NanoSpice Giga big ass capacity parallel SPICE.  Did 576 M
  element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
  layout SRAM.  Does 1+ B elements for 16/14/10/7nm FinFET or 28nm
  FD-SOI.  10X faster vs. parallel SPICE.  Dolphin and Attopsemi users.
  (booth 1219)  Ask for Lianfeng Yang.  Freebie: cell phone clip

      - John Cooley's Cheesy Must See List for DAC'16


From: [ Jason Xing of ICScape ]

Hi John,

DAC 2016 was 11.5 months ago.  We had a successful show and received a lot
of interest on our products.  However, I am not very happy with one thing
you did before that conference.  The reason is that when you compiled your
Cheesy Must See List for DAC goers you ignored what I sent you on one of
our main products.  This is partially what I sent you:

YOUR COMPANY: ICScape / Huada Empyrean Software

YOUR TOOL: ALPS -- "Accurate Large-capacity Parallel Spice"

WHAT TOOL(S) IT COMPETES AGAINST: Mentor BDA AFS, Cadence Spectre/APS,
Synopsys HSPICE

WHAT IS SPECIAL THIS YEAR ABOUT THIS TOOL AT DAC: We implemented a
breakthrough SPICE matrix solver, which enables a faster post-layout
SPICE simulation for large advanced node designs...

WHAT SPECIFIC USER COMPANIES USE YOUR TOOL: ...


What happened?  You didn't believe we built a fast true SPICE simulator, or
is it that we are coming from nowhere?
          
Or did you not wish to anger Mentor BDA, Cadence, and Synopsys?  You even
listed Silvaco and ProPlus, but why not us???

I would like to tell you more information about ALPS and hope it can change
your perception of our SPICE.

ALPS stands for Accurate Large-capacity Parallel Spice, which is a fast
circuit simulator with true SPICE accuracy.  Technology wise, ALPS uses a
breakthrough matrix solver to speed up the basic operations of circuit
simulation.

This enables much faster simulation for big post-layout designs below 28nm.
Based on the customer benchmark results, our ALPS achieves on average 2-5X
speedup over the 3 competing true SPICE simulators.  Some data points:

  - A charge pump block with 200K transistors and 15 million RCs
    in FinFET node ==> 11x speed-up than competitor 1

  - An OTP IP block with 3 million transistors and 30 million RCs
    in 40nm ==> competitor 1 failed to load in the netlist

  - A Serdes PLL with 20K transistors and 1 million RCs. 
    ==> 6x speedup over competitor 2

  - An ADC with 4K transistors and 600K RCs ==> 8x speedup over
    competitor 2

  - A DAC post-layout design 
    ==> 18x speedup vs. competitor 2, and 8x speedup vs. competitor 3.

You may wonder how does ALPS get such speed-up over other simulators, so let
me give you a high-level explanation.  Almost all parallel SPICE simulators
use a combined LU-decomposition and GMRES method to solve the circuit
equations, mainly for two reasons:

    - Circuits are partitioned into many blocks. For each block the
      internal matrix is extremely sparse, where LU-decomposition
      is the most efficient method to solve it.

    - The matrix for the block coupling nodes is dense, for which
      GMRES is the most efficient method.

A major flaw of the GMRES method is it needs an efficient pre-condition
matrix, otherwise it will converge very slowly or cannot converge at all.
It is very tricky to select a good pre-condition matrix.  And even with
a good pre-condition matrix, it often takes 5 to 10 iterations to solve
the equations successfully.

Our breakthrough in ALPS is that we have developed several new techniques
that can not only get a very efficient pre-condition matrix, but also
enable GMRES to converge very quickly in most cases -- therefore greatly
reduce the time for solving the equations.
      
So far ALPS has over 20 paid customers, and 30 customers evaluating it.
Compared with other true SPICE simulators, ALPS gets a 2-3X speed-up for
pre-layout SPICE simulation and 4-5X speed-up for post-layout SPICE
simulation. 

We really hoped that you had put ALPS in your Cheesy List in DAC 2016.
You can imagine what a great help it can be if a designer can reduce the
post-layout simulation time from nearly 1 week down to 1 day with ALPS.

We would like to have our customers to tell the performance and accuracy
stories.  We are working with them and will send you such stories when
they are ready. 

Thanks and feel free to call if you have questions.

    - Jason Xing
      ICScape / Empyrean Software                San Jose, CA

P.S. If I send you a Cheesy FORM for our ALPS simulator, will you
     please list it in your upcoming DAC'17 Cheesy List?  :)

         ----    ----    ----    ----    ----    ----    ----

Related Articles

    Industry Gadfly -- John Cooley's Cheesy Must See List for DAC'16
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    246 engineers on today's SPICE use vs. their future SPICE use

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