( DAC'16 Item 2 ) ----------------------------------------------- [12/16/16]
Subject: BDA, Solido, MunEDA, and Silvaco get #5 for Best EDA of 2016
RAVI STILL LIVES IN AN AIRPLANE: Last year, this is how I explained why the
world's oldest EDA tool, the SPICE simulator -- invented 43 years ago waaaay
back in 1973 -- is still a very hot commodity today:
"Here's the math:
start with 1000's of std cell, mem, analog/RF elements (1,000's)
TIMES number of specs per element (pwr, slew rate, gain, rise time)
TIMES number of fabs they're using (TSMC, GF, Samsung, SMIC, Intel)
TIMES number of processes per foundry (32nm, 28nm, 16nm, 14nm, 10nm)
TIMES number of variants per process (LP, HP, ULP, HPM, HPC, HPL)
TIMES number of PVT points (ff, 23C, 0.8 volt; ss, 40C, 1 volt; etc.)
TIMES number of Monte Carlo points (3 sigma, 5 sigma, 6 sigma)
all multiplied together equals why the IDMs, fabless, and fabs all
each buy 1,000's of SPICE licenses."
- John Cooley of DeepChip (DAC'15 #4)
And in that write up, I concluded with "... this is why Ravi Subramanian is
trapped in an aeroplane flying around the earth selling BDA AFS licenses."
Now the only thing that's changed is instead of 16nm, 14nm, 10nm... it's
moved on to 10nm, 7nm, 5nm... And Ravi still lives in an airplane.
BUT WHAT WILL CHUCK DO?: All of these AFS user responses were done in the
months following DAC'16 and before the recent Siemens/MENT buyout offer.
Now the big wildcard here is what will Chuck Grindstaff, the Siemens bigwig
who will be the proposed new owner of Mentor will do. Chuck's response on
DeepChip was:
"... our intent after the acquisition closes is to compete
aggressively in the EDA market including against Synopsys and
Cadence. ... we learned a lot about Calibre, Tessent, Veloce,
Questa, and other key Mentor technologies. ... Siemens is
excited to make future investments in Mentor's key EDA
technologies so that those can grow even faster."
- Chuck Grindstaff, Chairman of Siemens PLM (ESNUG 564 #2)
Which was a relief for a great portion of the EDA customer base because it
meant Mentor wasn't going away -- but I got a few concerned comments from
the BDA AFS users. "Why wasn't AFS in his list of key MENT technologies?"
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MONTE CARLO CATFIGHTS: Ah, yes, the scourge of on-chip variation only gets
more painful the smaller the nodes you go; which is a boon for companies
like Solido and MunEDA because they happen to sell SPICE variation tools.
The only one grumpy cat here is Tom Beckley because he owns Cadence ADE-XL,
which is the dominant platform for full custom circuit design -- and what
irks Tom is his users are doubting the Cadence WCD way of Monte Carlo.
As a counter, Tom had his Virtuoso TeamADE guys put up a not-so-cryptic
attack blog on something they called "HSMC" which everyone in the custom
world knew was really "Solido HSMC" because Solido coined the HSMC term
which caused Solido to write a very vociferous and deeply technical reply
back to Tom's "TeamADE" on DeepChip in ESNUG 562 #5. HSMC? WCD? Or the
new Cadence SSS? It's still anybody's game which will one win; but judging
from the absence of user comments on the new SSS yet lots of user comments
on HSMC, it looks like Solido's leading so far.
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"OH, WOW, THEY'RE REALLY BACK!": At the 2015 DAC, Silvaco stunned everyone
by, after being away for 10 years, it came back! But this time instead of
it being Ivan's company, Silvaco was reborn with his 30-something year old
son, Iliya Pesic, at the helm as its Chairman.
And to balance the energy of a 30-something, they very cleverly picked an
older 50-something guy, Dave Dutton, be the new CEO of Silvaco.
My only problem with Dutton was that he was a foundry guy, not an EDA guy.
So on first impression he could talk up a storm about fab processes and
wafers and steppers and dicing -- but he didn't know squat about EDA!
At the time, I estimated Dutton would last 3 to 6 months in EDA and then
he'd suddenly leave "to pursue other interests". Oh, man, was I wrong!
In the 18 months since that DAC, Silvaco's been very busy:
- acquired Invarian for it's concurrent PVT tools
- TSMC certifies InVar for EM/IR for 16nm FinFET+
- teams up with Chinese & Japanese universities for TCAD
- acquires Infiniscale to do variation-aware SPICE
- Ricoh adds 0.35um analog PDK support for Silvaco
- their Clever extractor beats StarRC at 7nm at MediaTek
- signs up a distributor in India
- Silicon Creations buys Silvaco layout & SPICE for 10nm
- Dolphin Integrations buys Infiniscale Variation Manager
- STMicroelectronics buys Infiniscale Variation Manager
- acquires edXact for parasitic reduction & netlist tools
- TSMC qualifies SmartSPICE for 7nm
- acquires Warren Savage & IPextreme to do IP stuff
- announces FlexCAN automotive IP with NXP
- joins the SOI Consortium
- expands a bunch of stuff in the Silvaco TCAD tools
- joins EDAC
- Raul Camposano joins Silvaco tech advisory board
- acquires Austrian company "Global TCAD Solutions"
- announces MIPI I3C IP made with NXP
So it turns out that I was wrong. Silvaco's not just "back", it's REALLY
back. And my guess is Dutton's not leaving Silvaco any time soon...
"Well, I'm still here. Didn't have to go to rehab,
and I'm not broke."
- Jimmy Buffett, American singer (1946 - present)
"Here I am, I still go on, you know, like the tides."
- Angela Lansbury, American actress (1925 - present)
QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen this year? WHY did they interest you?"
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SILVACO SMARTSPICE
We used Silvaco 15 years ago -- Ivan Pesic, the owner and CEO,
personally came down on-site and helped train and set up their
"Silvaco Utmost IV" device characterization/modeling tool.
I met with Ivan's son Iliya Pesic after he took over Silvaco. He had
been working in another industry, and made the transition to Silvaco
after his father's death. Iliya absolutely has the company migrating
in right direction now.
Silvaco SmartSPICE recently caught our attention again, because of
it's speed and accuracy claims. SmartSPICE maximizes the use of
your hardware parallel processing, so the speed up you will get will
be based on the number of licenses/accuracy you have or desire.
You can vary how you use SmartSPICE with the use of various
configuration/setups. For example:
- PLLs. It normally takes forever to get your PLL simulate
accurately -- they are notorious for taking hours and hours to
simulate. So you need both accuracy and speed. SmartSpice is
designed to fit your needs.
- Standard cell library characterization. Each standard cell
might have 20-40 transistors. Because they are so small, you
might want to run 12 simulations in parallel. Getting massively
parallel simulation with accuracy is very useful.
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We've been using Silvaco SmartSPICE simulator for over 10 years. It
was always very accurate, but has fallen behind in speed in the last
couple years.
We are expecting Silvaco to release a new version by the end of the
year that will compete in speed with the leading simulators and looking
forward to evaluating its capability.
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SILVACO EDXACT
Silvaco EdXact seems like a promising solution for parasitic reduction
which will also help to reduce our simulation time.
We've evaluated similar tools from other vendors without success, and
look forward to getting better results when we evaluate Silvaco as an
option.
---- ---- ---- ---- ---- ---- ----
We are interested in Silvaco EdXact (post-layout netlist
analysis/optimization)
Note: we don't have these tools in our company, so I don't have direct
experience to share at this stage.
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SILVACO ACCUCORE
Silvaco has a good tool with its Accucore SRAM characterization. It
competes with Synopsys SiliconSmart.
We do characterization so infrequently that unless it's broken, it's
hard to justify switching though.
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Silvaco's AccuCore XT SRAM characterization tool appeared to be
well-thought out. I was really impressed.
Accucore XT is built for large memory block level memory
characterization, such as SRAMs and large register files. If you have a
block with 1M gates, it will create necessary .lib, .v, and other
timing files needed for place and route and other high level simulation
and analysis capability.
Silvaco's Single Event Upset (SEU) module in the Accucore/Smartspice
stood out. Depending your product voltage levels and technology, your
memory can be vulnerable to bit SEU (Single event upset) errors due to
neutrons and particles. The SEU module is the only one of its kind in
the industry.
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SILVACO VARIATION MANAGER
Silvaco was talking about their Variation Manager product running a full
netlist and doing 6 sigma+ analysis.
It stretches possibilities to do both of them at once, and Silvaco
didn't discuss how they did so. Are they doing netlist pruning or some
dynamic sampling algorithm? I'd like to understand more to know if this
is real.
I don't see that Silvaco Variation Manager does any hierarchical high
sigma analysis. For memories, this would be important. For example, if
we instantiate one memory 500 times, does the tool's chip-wide analysis
account for it?
It looks like Silvaco has some "early in-design process" analysis,
called Variability Explorer Analysis (VX). For some studies, such as
sense amp and bit cell studies, it's good to do upfront analysis in
memory design -- both individually and in combination.
---- ---- ---- ---- ---- ---- ----
We looked at Silvaco Variation Manager at DAC.
Silvaco claims they do really well in high sigma design. However, we
work at 4 sigma, so we don't plan to look further.
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SILVACO INVAR
We saw a demo of Silvaco InVar. It seems like a competitive option to
supplement Apache Totem and Cadence Voltus. We plan to evaluate it
soon.
---- ---- ---- ---- ---- ---- ----
Silvaco InVAR Prime. The way InVAR showed hotspots was good.
It also had a good user interface, and looked easy to use:
- Early analysis of supply networks
- Finding and fix missing vias
- Current density estimates
I'd like to know more about how it correlates with RC extraction.
---- ---- ---- ---- ---- ---- ----
Silvaco InVar & InVar Prime Power Integrity.
Quick solution for power analysis
---- ---- ---- ---- ---- ---- ----
Silvaco InVar EM/IR
Been looking at Silvaco's InVar EM/IR electro-migration capability.
It appears to satisfy what we need at a high level, so we want to
take a closer look.
The biggest limitation for most flows is they don't integrate simulation
data with layout data. You need to have the transient simulation or
time domain simulation to get the specific current. I.e. you need
exact information rather than just device sizes and metal width.
Silvaco claims you can to use their simulation tool to get data and
their metallization data from their layout tool. We'd need to verify
it.
We compared Silvaco's flow to our own flow, and at a high level we see
no issues. However, it would have to be very compelling to make a jump
to their flow, vs just switching out one tool.
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MENTOR BDA AFS
For our 7nm and 5nm we buy BDA AFS licenses in bulk.
---- ---- ---- ---- ---- ---- ----
BDA AFS is our workhorse SPICE simulator.
---- ---- ---- ---- ---- ---- ----
Wally got a good deal with Ravi and AFS.
---- ---- ---- ---- ---- ---- ----
BDA AFS. I know it's boring, but I like it.
---- ---- ---- ---- ---- ---- ----
Mentor BDA AFS. Actually Ravi's AFS. He and his people make the
one SPICE we trust.
---- ---- ---- ---- ---- ---- ----
BDA AFS is definitely one of our top 3
---- ---- ---- ---- ---- ---- ----
Greg and Wally got a steal when they picked up AFS.
---- ---- ---- ---- ---- ---- ----
BDA AFS. Great support. Ravi is flying in to see us this week.
---- ---- ---- ---- ---- ---- ----
MENT AFS
---- ---- ---- ---- ---- ---- ----
For the quality runs, AFS.
For the cheap runs, Spectre.
---- ---- ---- ---- ---- ---- ----
BDA AFS and Cadence Spectre in ADE. Same as the last 2 years.
---- ---- ---- ---- ---- ---- ----
Spectre-XPS and Altos. We design memory circuits.
---- ---- ---- ---- ---- ---- ----
Depending on the pricing, we may go back to being a Spectre house.
(I don't believe I just said that.)
---- ---- ---- ---- ---- ---- ----
Still use Magma FineSim.
---- ---- ---- ---- ---- ---- ----
FineSim Pro
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Synopsys HSIM -- old Nassda customer here.
---- ---- ---- ---- ---- ---- ----
Cadence Spectre-APS and Berkeley AFS.
---- ---- ---- ---- ---- ---- ----
Cadence Spectre-XPS and Cadence Altos. We do memory.
---- ---- ---- ---- ---- ---- ----
AFS Mega. Our memories have over 40M elements.
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SOLIDO VARIATION DESIGNER
We design in FinFET. We use Solido Variation Designer to remove the
pessimism from our design corners, and to trade power and performance.
Using standard Monte Carlo on our circuits was infeasible both in
terms of run time and # of SPICE licenses required.
What we liked about Solido:
1. You can generate simulation corners appropriate for each individual
circuit, including the local and global variation, for circuit
optimization and to perform the correct tradeoffs on your circuit.
We need circuit-specific corners because sometimes standard corners
are too pessimistic -- or they cannot cover a spec at all in other
cases.
2. You can use those corners in what-if scenarios, using Solido Design
Sense to optimize the circuit. We can modify our design across a
range of device sizes -- across as many devices in the circuit we
have simulation time for. This lets us see the sensitivities and
gradually adjust the specs to optimize our circuits.
3. You can identify critical devices and process parameters that are a
concern for your specific circuit.
4. Sometimes the dominant factors Solido identifies are a surprise
(e.g. contact resistance) especially for lower feature sizes. The
Solido tool helps you avoid using extra power by making the device
bigger without a performance hit.
5. Easily analyze what-if circuit changes. Can visualize results of
circuit changes for best decisions on power/performance tradeoffs,
and to visualize those tradeoffs. (It's beyond looking at just
a set of numbers.)
For one high-speed circuit that I worked on, Solido helped me to:
- Cut evaluation time by about 30% for a 3-sigma corner
- Simultaneously reduce the circuit's power by 30%
- Improve latch sensitivity 50% from a previously-tuned design
Running 1,000 different combinations of the devices across 10 different
corners at 2-3 hours/simulation took:
- Solido: 1-2 weeks
- Standard Monte Carlo projected time: ~3 months
Solido also reduced the number of corners we needed to characterize our
design from our typical set of corners.
---- ---- ---- ---- ---- ---- ----
My company designs power and performance optimized memories and memory
compilers, including at 22nm, 14nm and 7nm. Variation aware design is
important for us to maximize yield, especially as we drive reuse of
our IP.
We use Solido Variation Designer for our high-sigma analysis. We have
an intense drive towards performance, power and area.
Solido HSMC:
- Runs a random sampling
- Uses the data from that sampling to calculate or build a model.
- Uses the model to build an ordered list of simulation points,
simulating the one it thinks is going to be the worst first, and
then the next one second, etc. Focusing the SPICE simulations on
the tail of your distribution that you're most worried about.
- Reports the actual ordering and compares to the model ordering
so you know HSMC is picking the right points in the tail of the
distribution.
Instead of using Solido, you could do a small number of samples using
regular Monte Carlo to get a sigma value, then extrapolate. However,
simulating at the tail you can see that it's a curve and not actually
straight. Circuits don't respond the same way to variation out on the
tail of the distribution as they do around the center of the
distribution. That error would either come in the form pessimism,
leaving performance or area on the table or even worst, yield loss.
So it's important that Solido actually does the simulation of the points
out in the regime where you're worried.
Solido has more than just this high sigma capability:
- It gives you good feedback in terms of which specific devices
and parameters are actually driving your yield loss
- It enables you to focus in and optimize specifically on those
particular devices, with valuable information in terms of which
device is actually having that yield impact.
- It has a very good queuing management. When you're dealing with
a lot of jobs, this is critical.
- It can do excellent PVT sweeping with the intuitive GUI, again
leveraging queue management.
---- ---- ---- ---- ---- ---- ----
We use Solido Variation Designer to solve memory issues for our SRAM
designs. Solido satisfied these requirements we had:
1. It's foundry calibrated. Our foundry bit cell logic device
simulations, etc. must match the TSMC foundry specs.
2. Speed and variety of circuits & circuit metrics it can be applied to
3. It reports the statistical SPICE simulations results in different
formats such as Excel sheets, ASCII text, PDF, etc.
4. Can automatically capture and analyze the statistical simulations
from multiple SPICE runs for various parameters across the entire
design hierarchy
- device level
- circuit level
- multiple circuit styles
We use it to help build low cost memory circuits that are fast and dense
with low active/retention Vmin and low currents.
---- ---- ---- ---- ---- ---- ----
We currently use Solido HSMC for high-sigma variation analysis. We also
have some in-house solutions that cover some of our other variation
design needs.
---- ---- ---- ---- ---- ---- ----
Solido Variation Designer looked interesting.
I think it can help improve yield without blowing up simulation time, or
using up lots of dollars on simulator licenses.
I especially appreciate that Solido invests a lot of effort in human
computer interface. Usually the "human" is the slowest part of the
design process, and anything that can speed that part up is welcome.
I wish the other EDA vendors would follow their lead. Also their demo
was on a real circuit, not just a two stage op-amp.
Disclaimer: I've only seen a demo, and have never used their tool.
---- ---- ---- ---- ---- ---- ----
Solido Variation Designer - Solido gave an introduction of tool usage.
We are interested in using the tool to estimate the cell speed
impacted by OCV.
---- ---- ---- ---- ---- ---- ----
Solido is the best tool in the market for variance especially for
memory type of IPs. They still need to enhance their algorithms
for handling complex IPs in a better way.
---- ---- ---- ---- ---- ---- ----
Solido Variation Designer
We use Solido Variation Designer Fast MC. One of the things we really
like about Solido is that they make it easy for designers to understand
and use during design.
- Solido's user interface gives simple questions to follow. Then
we can go deeper with the "advanced" tabs if we want.
- Solido is much easier than MunEDA.
Without an advanced tool such as Solido, engineers assume Gaussian
distributions to keep the analysis simple; this assumption is often
wrong. Solido's multi-modal capabilities give us more confidence.
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MUNEDA WICKED & CADENCE ADE-XL
I'm German. Of course we use MunEDA.
---- ---- ---- ---- ---- ---- ----
MunEDA WiCkeD.
We use their RSM for generating performance models for our macro
cells as well as their optimizers for sizing of our RF circuits
in combination with Keysight GoldenGate simulator. We are also
using Eldo simulator from Mentor Graphics for other low frequency
analysis and sizing of IC's.
---- ---- ---- ---- ---- ---- ----
MunEDA Wicked
resizing FEA, DNO, GNC, YOP
reliability CED, WCO, BAS, FEA, DNO
---- ---- ---- ---- ---- ---- ----
MunEDA Wicked for memory cell design
We're strong believers of WCD analysis for Monte Carlo
---- ---- ---- ---- ---- ---- ----
MunEDA Wicked
Our CTO doesn't trust the sample errors in HSMC. He wants
us to stick with WCD instead.
---- ---- ---- ---- ---- ---- ----
MunEDA WiCkeD.
We have done evaluation and trials of the tool recently.
We found that the tool analysis functions allow to get a quick
and good insight of the circuit critical parameters. Also we
could perform optimization of simple and complex analog circuits
over several constraints with good results and speed.
We plan to add it to our analog design flow.
---- ---- ---- ---- ---- ---- ----
MunEDA WiCkeD is integrated since many years in our low power
IC Design Flow for car multimedia/radio chips. From our point
of view it is the best on the market for high-sigma analysis
and circuit optimization. We are running it with Eldo
---- ---- ---- ---- ---- ---- ----
Most interesting tool at DAC was the WICKED tool set from Muneda.
We are going to evaluate it soon. It offers process porting
assistance as well as promising optimization algorithms which
are not restricted to a specific design framework from Mentor,
Cadence, nor Synopsys. It's sensitivity analysis seems to allow
good computing efficiency and easy user control.
---- ---- ---- ---- ---- ---- ----
MunEDA WiCkeD high-sigma analysis and circuit optimization. Great
interface, remarkable results and data management.
It is integrated in our worldwide AMS design flow since more than
10 years and used in several hundreds of design and tape-out projects.
WiCkeD is supporting all of our Smart Power, CMOS and NVM technologies.
They significantly improved their tools regarding very large circuits
capacity and runtime efficiency that increased by factors 10x-50x
depending on the single tools.
---- ---- ---- ---- ---- ---- ----
WicKeD tool from MunEDA. My group has using it with sucess for
optmizing our circuits for radiation hardening and reliability.
---- ---- ---- ---- ---- ---- ----
Virtuoso ADE-XL
WCD is what's real. Don't believe those Solido lies.
---- ---- ---- ---- ---- ---- ----
Cadence ADE-XL with Spectre
---- ---- ---- ---- ---- ---- ----
Yet to be determined.
Every few weeks we have internal arguments about Solido HSMC against
Cadence and MunEDA WCD. Now Cadence does SSS making matters worse.
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