( ESNUG 568 Item 2 ) -------------------------------------------- [03/17/17]
Subject: SCOOP -- more detailed leaked HiSilicon 16FF+ IC Compiler II data
Enclosed are 8 slides from the Synopsys IC Compiler II DAC'16 lunch. It
appears to be a short talk by Huwaei (HiSilicon) engineers about how they
designed their Kirin 955 processor in TSMC 16FF+ quad ARM Cortex A72's and
quad ARM Cortex A53's, at 2.5Ghz/1.8Ghz.
- "leaked HiSilicon 16FF+ ICC2 slides from DAC'16"
From: [ John Cooley of DeepChip.com ]
Here's 15 more slides detailing the HiSilicon Kirin 955 tapeout as initially
earlier described in ESNUG 568 #2. Enjoy!
- John Cooley
DeepChip.com Holliston, MA
P.S. If *anyone* has anon comments they want to add to (or explain) any
of these individual slides, CONTACT ME. I'll edit in your insights.
(And say exactly which specific slide you're commenting on, please.)
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Slide 1 -- (click on pic to enlarge image)
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Slide 2 -- (click on pic to enlarge image)
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READER COMMENTS: Looks like DC Graphical is being used.
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Slide 3 -- (click on pic to enlarge image)
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Slide 4 -- (click on pic to enlarge image)
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Slide 5 -- (click on pic to enlarge image)
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Slide 6 -- (click on pic to enlarge image)
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Slide 7 -- (click on pic to enlarge image)
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READER COMMENTS: Slide says IC Compiler. Isn't this an IC Compiler II
tapeout?
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Slide 8 -- (click on pic to enlarge image)
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Slide 9 -- (click on pic to enlarge image)
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Slide 10 -- (click on pic to enlarge image)
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Slide 11 -- (click on pic to enlarge image)
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Slide 12 -- (click on pic to enlarge image)
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Slide 13 -- (click on pic to enlarge image)
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READER COMMENTS: Again it says IC Compiler. Isn't this an IC Compiler II
tapeout?
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Slide 14 -- (click on pic to enlarge image)
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READER COMMENTS: Now it says IC Compiler II?
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Slide 15 -- (click on pic to enlarge image)
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READER COMMENTS: ICC used mostly. Only last 2 slides mentioned ICC2.
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Related Articles
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ICC2 patch rev, Innovus penetration, and the 10nm layout problem
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