( ESNUG 422 Item 6 ) -------------------------------------------- [02/19/04]
Subject: ( DAC 03 #34 ) A Detailed User Critique Of Silicon Canvas Laker
> Laker's big benefit is speed on StreamIn. 20%-30% faster than Virtuoso.
> Panning, redrawing and going to the coordinates are quick tasks. Don't
> feel pain on Laker; a little pain on Virtuoso.
>
> Laker's Hierarchical NetTrace really helps to find out layout problems
> and it's very quick. I don't remember Virtuoso has this function.
>
> The User interface is very similar between Laker and Virtuoso. I mainly
> use Calibre-RVE and the setting is already in Laker, but need to setup
> by myself in Virtuoso.
>
> - from http://www.deepchip.com/items/dac03-34.html
From: Arturo Gonzalez <art.gonzalez=user domain=amd spot calm>
Hello John,
You asked if I could send you a customer feedback survey regarding Silicon
Canvas' Laker software. The following observations and comments are from
my colleagues and myself and cover a wide-range of features.
A. Schematic
In general, it was difficult to import a Virtuoso netlist to Laker. One
netlist in particular needed extensive hand-editing prior to exporting
to Laker.
1. Create Map File
A map file is a prerequisite prior to exporting a netlist from
Virtuoso to Laker. This file is vital since it contains the mapping
elements necessary for Laker to "recreate" the Virtuoso schematic and
to be able to create a layout cellview. Depending on the number of
different devices that need mapping, it can take a while to create the
map file (from scratch) and to create it correctly. A generic map
file could cover many devices in many different schematics.
2. Unreadable Binary Netlist
When Laker imports a Virtuoso netlist, it automatically creates a
"binary" netlist which is non-readable. The user must export this
binary netlist to create a readable CDL(Circuit Design Language)/SPICE
netlist file.
3. Parameter Inheritance
Laker cannot handle parameter inheritance!
In Virtuoso, Parameter Inheritance is the hierarchical relationship
between the parameters of a device at the current and lower levels.
Basically, the parameters of a device are passed down or "inherited"
to the lower level devices. Think of an inverter symbol that has
length and width parameters. These parameters are inherited down to
the pmos and nmos devices.
One schematic in particular used an inverter w/ parameter inheritance.
In the netlist, this inverter was listed in the sub-circuit of another
device. I had to manually add the parameter inheritance expressions
to the inverter in the sub-circuit for Laker to recognize it!
Graphically, in the schematic under this situation, the inverter
symbol would be repesented by a "box" instead of the familiar
inverter symbol.
B. Stick Diagram
At first, the stick diagram feature seemed like an exciting feature to
try out. Unfortunately, it fell short of expectations.
1. Device Hierarchy Problem
The stick diagram will not generate devices with hierarchy. One must
actually descend into the device symbol and select the "primitives"
for stick diagram representation.
2. 90-Degree Device Labels
Reading 90 degree device labels on the gates was no fun. Perhaps
Laker can have a pop-up window appear when the cursor is placed on a
device. This pop-up window could list the device name horizontally.
3. Unrealistic Device Abstracts
The devices in the stick diagram are of the same width and length.
Realistic abstracts with true width and length parameters would have
been more helpful for floorplanning.
4. Device Flip Feature Requested
It was frustrating not being able to flip (not "swap") a device from
left-to-right and vice-versa since this feature is not available.
5. Find Function Requested
A device "find" function would also be very appreciated. I had to
zoom in and scour the 90 degree labels on the devices to find my device
of interest.
6. Print Feature Requested
There is no "print" feature. There were several times that I wanted
to print my stick diagram floorplan but couldn't. I wound up using the
"snapshot" feature of my Unix environment for printing.
7. Cannot Delete Highlighted Net
Highlighted nets won't delete when depressing F8.
8. Merge Gates Feature Requested
There is a merge feature for devices but not for gates.
9. Unrealistic Wiring
I know that the wiring connections in the stick diagram show
connectivity to devices only and do not represent any particular metal
layers; however, for floorplanning, being able to assign specific
metal layers to the wires would be more realistic. When drawing
stick diagrams with colored pencils, a layout designer will more than
likely use different colors to represent different metal wires. Why
not with the Stick Diagram Tool?
After having worked with Cadence's Virtuosos XL software for a few weeks, I
wonder if the Laker Stick Diagram tool is really necessary. The XL software
will realize devices directly from the schematic to the layout cellview with
the "Gen from Source" and "Pick from Schematic" features.
C. Cell Template
Cell Height
I was trying to create a standard cell with a specific cell height. In
the Cell Template form, Cell Height is not a user-defined field but
rather the resultant of the summation of several parameters. It was
really difficult to manipulate these parameters and to try to attain a
specific cell height for my standard cell.
A user-defined cell height would have allowed me to try and "tune" the
parameters to meet my standard cell height.
D. Layout
User-defined Fold Pattern
Traditional device folding has the output in the middle and the inputs
(i.e. vdd) on the outside. For example, a device folded once to create
two stripes would have the output on the middle node and the inputs would
be on the outside nodes.
The Laker software has folded devices with the output node on the outside
and the input node on the inside. User control over the fold pattern
would be useful.
E. Wire Routers
Point-to-Point (PTP) Router
This feature is really neat and a very strong feature for Laker! One
defines source and target connections and the router will connect both
points. Dependencies include user-defined criteria such as metal layer
direction costs (horz or vert), design rules, etc. The user may use the
fully automatic PTP mode or the semi-automatic mode for more control.
This feature was especially appreciated at the big block level.
For small cells, it was not very productive, especially when trying to
connect multiple gates in poly. More often than not, there was no
orderly placement of poly to connect the multiple gates which shot the
frustration factor up quickly.
Bottom line is that the Laker software program will primarily be a value
add for block wiring ECOs where the PTP router can be fully utilized.
- Art Gonzalez
Advanced Micro Devices Austin, TX
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