( ESNUG 412 Item 1 ) -------------------------------------------- [05/22/03]
Subject: ( SNUG 03 #5 ) 5th Grade Math, Architectural Weenies, and SystemC
> BATTING 500: If Aart de Geus was a baseball player, he'd be batting 500
> these days. Looking at the survey data, it was almost creepy weird to see
> that out of the 38 people who commented on System Verilog, only 3 thought
> it's a bad idea. Do you have any idea how rare it is to have 92% of users
> agree with *any* stance in the EDA world??? Whoa! But, just to make sure
> that Aart doesn't get too cocky, for the third year in a row, his RTL/gate
> customers have again (SNUG 02 #7) very loudly voiced how they absolutely
> *hate* the idea of designing chips using SystemC. To be fair, tho, some
> of the architectural weenies seem to have embraced SystemC. But in EDA
> business terms, there's 1 architectural weenie for every 250 RTL-level
> engineers (i.e. you don't make much money in EDA helping the weenies.)
> Intel has what? A few dozen architectural weenies? And how many tens of
> thousands of implementation engineers? Where's the most EDA money here?
>
> - from http://www.deepchip.com/items/snug03-05.html
From: Brett Cline <bcline=user company=forteds grot con>
Hi, John,
With regards to your SNUG Trip Report section on System Verilog and SystemC,
you might want to pull out your 5th grade math book to review the chapter
on percentages. I was impressed that you were able to compute that 35 out
of 38 is ~92% -- except there were only 36 total survey responses. Plus
you jumped from saying that 3 users disapproved of System Verilog to stating
that the remainder approved -- while in fact a large number had no comment
or were neutral. In reality, 18 of the 26 respondents who actually
commented on System Verilog in your survey were net positive, which was a
69% approval rate - not 92%, but still very respectable.
For SystemC, 12 of the 29 people who commented were net positive, which is
also a respectable approval rate of 41% -- especially for your readers, who
are primarily Verilog/RTL designers. This 41% is two orders of magnitude
away from your conclusion of a 1/250, or 0.4% potential usage for SystemC!
Everyone knows that a statistician can use data to make any argument they
choose, and your contrasting trip report conclusions on SystemC and System
Verilog show that your skills are particularly impressive. When the ESNUG
gig runs out, this talent will be handy for a marketing or perhaps as an
Iraqi information minister position. Or perhaps your eyes were just crossed
from looking at so many survey responses at the time?
On a technical standpoint, the two languages are complementary. No one is
going to throw away RTL implementation languages like Verilog and System
Verilog to write RTL in SystemC. SystemC is meant to permit a single
language to be used for specification, architectural analysis, verification,
and ultimately behavioral design. It is mostly used today for designs that
start off as complex algorithms, typically C or C++.
So why not just use System Verilog w/ DirectC rather than SystemC? Because
System Verilog, even with a C interface, simply doesn't provide an
additional abstraction level nor any real productivity benefits for a
designer. C/C++ algorithms have no set timing and they cannot easily be
mapped to hardware blocks because they lack a protocol interface. So those
who attempt to use the System Verilog C interface will find it doesn't
include hardware design prerequisites such as concurrency, hierarchy, and
interconnect. In contrast, SystemC adds the necessary fundamental high-
level design functionality such as hierarchy, cycle accuracy, and bit
accuracy to the C algorithms. For any of the "0.4%" that are interested,
we have made an introductory training class available for free on our web
site.
As for making SystemC viable moving forward, it will be the same as with
any design language. Tool support, especially synthesis, will be the key.
As the new generation of behavioral synthesis products matures, the high-
level model that the 'weenie in the corner' creates will suddenly look
like the starting point for hardware design. Those 'architectural weenies'
(as I believe you referred to them) that are forward thinking enough to be
seriously evaluating SystemC, are the start of a new breed that will one
day be the mainstream designer.
I'm sure at least "92%" of people agree with me - but I guess that depends
on how you count it, John.
- Brett Cline, Marketing VP
Forte Design Systems San Jose, CA
Editor's Note: Sorry about this, Bret, but once I saw all those customer
letters that were overwhelmingly pro-System Verilog, I just counted them
up and stopped cutting & pasting them in the report. Instead I just
started cutting & pasting all the more interesting SystemC comments. So,
Bret, my 92% pro-System Verilog stat really does hold. And although I
never counted them, I found 12 pro-SystemC to 20 anti-SystemC comments.
That's a 38% approval rating for SystemC -- but if you go and read them
you'll see they're all SystemC-for-architectural-weenies letters:
"The SystemC is ideal way for architecture exploration. My reality is
how to convince my boss to allocate the extra resource and schedule for
this type of works when our fundamental architecture is already in
placed. I think SystemC requires designer to develope extra special
skill sets."
- James Wang of Xiran
"We will be using SystemC for architectural exploration simulations."
- David Lau of PMC-Sierra
"We are using SystemC, mainly for system modeling and architecture
prototyping."
- Wilson Chan of Qualcomm
"I've been using SystemC for some modeling, now using it for
verification (with verification library). Probably switch to
System Verilog when available. Will never ever ever (at least not
until next year) use any flavor of C for hardware design."
- Brian Schaufenbuel of LSI Logic
The I-hate-SystemC letters came from people who implement real chips for
a living. So I still stand by my original comment that there's much more
money in selling to 30,000 implementors vs. 2,000 architects. - John
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