( SNUG 03 Item 5 ) ----------------------------------------------- [05/14/03]
Subject: System Verilog (Superlog), SystemC
BATTING 500: If Aart de Geus was a baseball player, he'd be batting 500
these days. Looking at the survey data, it was almost creepy weird to see
that out of the 38 people who commented on System Verilog, only 3 thought it
was a bad idea. Do you have any idea how rare it is to have 92% of users
agree with *any* stance in the EDA world??? Whoa! But, just to make sure
that Aart doesn't get too cocky, for the third year in a row, his RTL/gate
customers have again (see SNUG 02 #7) very loudly voiced how they absolutely
*hate* the idea of designing chips using SystemC. To be fair, though, some
of the architectural weenies seem to have embraced SystemC. But in EDA
business terms, there's 1 architectural weenie for every 250 RTL/gate-level
engineers (i.e. you don't make much money in EDA helping the weenies.)
Intel has what? A few dozen architectural weenies? And how many tens of
thousands of implementation engineers? Where's the most EDA money here?
"We use Vera and VCS. System Verilog is actually a step backwards. I'd
like to see us do modeling with SystemC and move this technique down to
the RTL. But I don't see it happening here for a year or two."
- Curtis Jones of Hewlett-Packard
"System Verilog looks great on paper. However I really wonder if we'll
get all the tools in our flow to support it fully. For Verilog-2000
we were burned quite badly as either all tools in the flow didn't
support it or the support that tools added was partial (where is
generate?) Till all vendors support it fully we will keep relying on
our own proprietary preprocessing scripts to do the job."
- [ An Anon Engineer ]
"System Verilog is Verilog finally becoming a real language. I like it
a lot. Why can't I have it now? Oh. I can if I use VHDL."
- Arthur Nilson of Unisys
"If System Verilog leads to a single standard, great."
- Dave La Rosa of Microchip Technology
"I never liked SystemC. Too far of a paradigm shift for not enough
ROI. I was never sure which was the weakest or strongest reason
to try SystemC: 1) H/W vs. S/W (partitioning and co-simulation) or
2) HLL constructs for verification."
- Martin Gravenstein of Time Domain Corp.
"We do not see using SystemC - ever."
- [ An Anon Engineer ]
"This is working towards the right direction. In SystemC versus System
Verilog, I do think that System Verilog has a stronger case. More
people know and are more comfortable with Verilog."
- Bengt-Erik Embretsen of Zarlink Semiconductor
"I like the idea that Synopsys is trying to standardize on one super-set
language. I have concerns about it being truly backwards compatible
with Verilog. If I were using VHDL (I'm not), I would really be ticked
off. Another concern is how successfully they are going to be able to
pull off the introduction of tools that support System Verilog - if my
experience with Presto, a mere update of the verilog compiler, was
indicative, I think System Verilog could be a big disaster.
I see the evolutationary path of System Verilog much more attractive
than SystemC. I don't see myself using SystemC in 6 months and
probably not for a 1-2 years. I acknowledge that Verilog as a
verification language is quickly losing steam, but I don't want to
spend the time or bandwidth to try to do such a big conversion to
SystemC -- especially if the terrain is uncertain."
- Tomoo Taguchi of Hewlett-Packard
"Maybe using SystemC in 1.5 years. (I'd like to see synthesizable
signal's in VHLD packages.)"
- Ross Swanson of Flextronics
"System Verilog looks like a promising evolution for Verilog. I don't
know if SystemC is the right hammer for our nails so I'm taking more of
a wait-and-see on that one. I thought it was cool that Aart had the
balls to effectively squash VHDL."
- [ An Anon Engineer ]
"Personally, I am all for anything the eliminates SystemC and VHDL. If
System Verilog is it, then its fine with me! While my employer does
use SystemC, it is in very isolated (read: researchers that aren't
required to produce on a schedule or budget) and even then is
restricted to architecture/verification level work.
I think that anyone considering designing an actual device with SystemC
should be required to take an immediate psychological evaluation
and/or be forced to forfeit their college degree."
- [ An Anon Engineer ]
"I agree with Synopsys's view regarding SystemC. SystemC should only be
used for higher level abstraction. By only focusing on higher level
abstraction with the SystemC, many detail transitions are removed;
therefore, 100x simulation speed can be achieved and we are one step
closer to the reality of SW/HW co-simulation with real SW codes. I
don't see a need to develope RTL codes with SystemC. Implementing RTL
level code with SystemC does not give you any simulation speed
advantage. So if Verilog HDL is not broken, don't fix it!
The SystemC is ideal way for architecture exploration. My reality is
how to convince my boss to allocate the extra resource and schedule for
this type of works when our fundamental architecture is already in
placed. I think SystemC requires designer to develope extra special
skill sets."
- James Wang of Xiran
"We will be using SystemC for architectural exploration simulations."
- David Lau of PMC-Sierra
"SuperLog / System Verilog looks OK, but we are still using Vera and
Verilog. Does any of the big simulators really support SuperLog yet?
I do not think so, and until then it will not be taken very seriously."
- [ An Anon Engineer ]
"Cadence is off promoting TestBuilder, and their own environment, so I
don't see any support from them for System Verilog."
- Tom Thatcher, ex-Agilent and looking
"System Verilog looks like VHDL all over again, but perhaps better. I
sure am tired of not having access to the cool new tools (because we're
VHDL), and if System Verilog takes care of that for me, I could be
persuaded. Yes, I may use SystemC in the next 6 months."
- Ken Sailor of PMC-Sierra
"System Verilog is a good idea, and it has some very useful & necessary
features for writing better test benches, along with making designs
somewhat more 'parameterizable'. My only concern is that Accelera,
Synopsys, & Cadence work out the compatibility issues w/ Verilog-2001,
and that Synopsys for its part finally supports *all* of Verilog-2001
(and Verilog-95 for that matter.)
We haven't touched SystemC and aren't likely to in the next year."
- Kris Monsen of Mobilygen
"System Verilog adds lots of features for verification. I am starting
to use the OVA and OBC of VCS 7.0 in the next project. For the RTL
design, it is pretty much the plain old Verilog. SystemC is best for
architecture analysis. I don't see why to take the risk of using
SystemC for logic design."
- [ An Anon Engineer ]
"I see SystemC taking shape to be used in high level configuration, and
design. Sort of as a bridge between say a Comm-Systems & RTL designer.
Use SystemC to model high level behavior, and get rapid prototyping at
high level done without having to wait for VHDL/Verilog code to be
completed. I think there is still a lot of things to be done for RTL
to be verified against SystemC specs, such as we do formal verification
between RTL and Gates. That would be a very desirable tool to have."
- [ An Anon Engineer ]
"Last November, I was at the Cadence Users Conference the week before
Boston SNUG and took note of the disappointment expressed by many
Cadence panelists over the unexpectedly slow adoption of SystemC by
users. For those of us who have looked at SystemC and already
rejected it, this comes as no big surprise. I think some SystemC-like
techniques will migrate into the System Verilog design flow through a
standard Direct-C interface, and then EDA vendors will claim SystemC
victory in much the same way that the Verilog-VHDL 'wars are over and
we all won!'"
- Cliff Cummings of Sunburst Design
"I'm already seeing younger designers that have never worked with
gates or schematics, who write great behavioral code, but horrendous
HW descriptions. I expect SystemC will only aggravate this problem."
- [ An Anon Engineer ]
"Judging only by the draft specification, the System Verilog extensions
seem like a big help for system design, enabling object-oriented
design techniques. And yes, I would like to try (would consider using)
SystemC in a hardware/software design since the hardware would be
modeled using the same language and development tools as the software
part of the design. Don't know about the next six months, though."
- Bob Lisanke of Nontrivial Systems Corp.
"As mainly a verification engineer, I think System Verilog is going to
be a really good extension to Verilog, but I don't think we will see
a lot of tool support for it for a few years. My estimate is 3-5 years
for it to be mainstream.
I doubt I will ever use SystemC and really wouldn't want to."
- [ An Anon Engineer ]
"No plans to use SystemC."
- Patrick Allen of Infiniswitch
"We used the Superlog simulator from Co-Design at my previous company
and replaced VCS with it. Considering that it was not 100% complete at
that time, we were still very impressed with it and see Superlog/System
Verilog as the future of Verilog.
No interest in SystemC whatsoever."
- [ An Anon Engineer ]
"We are starting to use SystemC on our current design and if successful,
will use it for all new designs."
- [ An Anon Engineer ]
"VHDL is dead, someone please tell the Academics and European community.
System Verilog is the way to go as it extends Verilog to where one
unified language exists for test and RTL design. I would suspect that
both Vera and E will go away in short order once System Verilog becomes
standard, especially if the incremental tool cost is minimal
comparitive to the astronomical licensing costs that Verisity charges.
In the long run, it's more economical & efficient to have engineers
know one language that can address test and design simultaneously."
- Gregg Lahti of Microchip
"We use a Verilog PreProcessor (VPP) language here. Haven't used raw
Verilog for about 5 years. Our VPP was developed locally by an Agere
employee. Most of the features of it are now recently finding their
way into Superlog, Verilog 200x, System Verilog, etc. So at some time
we may be switching to one of those 'standards', once we see which
will/may survive.
We looked at SystemC about 2 years ago, and felt that it probably would
improve our simulation times, but we would have to re-code our whole
RTL. The SystemC translator was not up to the job, and with our VPP
it would have been some additional translation steps."
- Bob Lawrence of Agere Systems
"It's definitely good to have one single HDL. But I highly doubt VHDL
will go away because of these government projects. Uncle Sam won't
let it die.
System Verilog is advertised as the all-in-one language, but it's
actually a set of different languages (HDL, HVL, assertion). To
master the entire language is equivalent of learning a few different
languages. The only advantage of such unified language will be tool
cost. We just need to buy one simulator.
We are using SystemC, mainly for system modeling and architecture
prototyping."
- Wilson Chan of Qualcomm
"Excited about System Verilog for design and verification. Praying
that our European customers eventually see the light (won't be easy,
VHDL entrenched). Eagerly awaiting tool support for System Verilog.
I've been using SystemC for some modeling, now using it for
verification (with verification library). Probably switch to
System Verilog when available. Will never ever ever (at least not
until next year) use any flavor of C for hardware design. Somewhat
paradoxically, many European companies and academics are jumping on
the SystemC train for design(!!) and verification."
- Brian Schaufenbuel of LSI Logic
"I would be interested, as would the rest of us VHDL users, to hear more
about the System Verilog developments. If Accellera went along with
the idea - fine - we'll convert. I kind of feel like an outcast as a
VHDL user anyway, and it might be good to be all using the same
language. I'm a rather ardent VHDL supporter, especially because we
do our complex test benches in VHDL as well as our designs, so the same
guys do both. I only have 3-4 engineers, so adopting another language
for testbench development and having a couple engineers become
specialists in that language will ravage my design staff. I might as
well take two of my guys down the parking lot & shoot them in the head.
It's amazing to me how much work has been done over the years to
overcome the inadequacies of Verilog (pre-2001). How many languages
have come and gone, how many $100 K tools have been developed, how
much $$ has gone into marketing these products, all becuase Verilog
did not have all the features that VHDL has. The PLI was kind of a
band-aid, and even the simplest capabilites on a test bench required
use of the PLI, guys that can write PLI, new languages, drivers...
what a mess.
To me, the idea of using System Verilog as both a testbench and
verification language AND as a language for design (at least the
subset) makes alot of sense. What they could have done is simple
switched to VHDL several years ago. Verilog 2001 absorbed all the
good things from VHDL that it lacked, and now they want to enhance it
and also use it for verification and test bench development. In the
end they'll all say 'See? Verilog won!', when in fact it's just been
waking up and copying VHDL benefits. What a crock."
- David Frazer of Match Lab, Inc.
"I hate Verilog. I want to stick with VHDL and see enhancements there.
We do not use SystemC yet. But I think it's worth to get in deeper
contact with SystemC. I don't have a clear picture about System
Verilog yet."
- Markus Schutti of Infineon
"System Verilog:
+ synthesizable
+ can do HW/SW cosim (via PLI or DirectC)
- doesn't yet have all the high-level modelling features.
SystemC:
+ can do high-level models
- you have to write them
- not synthesizable
- if you write RTL-level code, it's as slow as System Verilog.
Conclusion: use System Verilog with DirectC.
Use VtoC from Tenison to convert to pure C, so all your SW guys can
simulate your RTL code. Also, there's a lot of use of DirectC for
things it was never meant to do; we're looking seriously into that
for cosim."
- [ An Anon Engineer ]
"I think that System Verilog will completely take over the market, but
that it will take longer than expected, maybe 2-3 years.
Note that System Verilog is a superset of Superlog: it also contains
a lot of assertion stuff from Vera.
I think that SystemC is dead."
- Dave Chapman of Goldmountain Consulting
"I like the System Verilog and SystemC languages. We use VHDL now for
RTL design and simulation. System Verilog would help our simulation
test bench effort (I'm sure it's a wash for RTL synthesis). I have
used SystemC successfully in the past, but I don't think we will use
it since our design is mostly evolutionary."
- Lance Flake of Maxtor
"I have no interest in SystemC."
- Matthew Henry of Agere Systems
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