( ESNUG 345 Item 10 ) --------------------------------------------- [3/1/00]

Subject: ( ESNUG 344 #8 )  Superlog, Maybe.  But C++ HW Design Is A Joke

> The problem with Superlog is that it's a new language.  Most designers
> know C today.  Why not take advantage of a universal language like C++
> and use it for both its ability to look like Verilog as well as its
> verification and design extensibility capabilities?
>
>     - Bill Steinmetz
>       Cisco Systems


From: Anders Nordstrom <andersn@nortelnetworks.com>

Hi, John,

I do not agree with Bill at all.  I don't see Superlog as a new language, I
see it as an evolution of Verilog.  You can use whatever language you like
as long as it is compatible with Verilog.  We are using Verilog exclusively
for design and verification and by now we have 50 million lines of Verilog
code that we are not going to replace.  I know some C but I am not using it
for design or verification, neither is anyone else that I know around here.
C++ is even more of an unknown!  Yes you can make C look like Verilog if
you are using some of the tools like CynApps but the designer have to
rewrite his code several time to make behave like Verilog and then what is
the point.  Surely there are instances where C is a better language, but
using C in isolation and trying to link it to a Verilog simulation via the
PLI I don't think is the right solution.  A much tighter coupling between
the two languages is required and ONE way of achieving that is SuperLog.

    - Anders Nordstrom
      Nortel Networks                     Ottawa, Ontario, Canada