( ESNUG 344 Item 8 ) --------------------------------------------- [2/23/00]

Subject: ( ESNUG 335 #9 )  Hey!  C++ Is The HW Design Language Of Choice!

> I shook my head in disbelief when I first read of the recent push to
> make C++ the basis for high-level synthesis tools.  C++ is totally
> unsuitable to this.  ...  C++ is a cumbersome, complicated language with
> myriad subtle pitfalls.  The language does so little to protect people
> from writing patently invalid programs that I can't image it's going to
> help people stay within the "synthesizable subset".   Large-scale
> structure is difficult to express and can be casually circumvented.
>
>     - Nick Okasinski, CAD Software Designer
>       SGI High Performance Microprocessor Group


From: Bill Steinmetz <bills@cisco.com>

I'm dumbfounded by some of the recent editorials in ESNUG regarding "C++
as an HDL language sucks".  This statement could not be further from the
truth.  In fact, reading such neanderthalic rhetoric has incensed me to
write to ESNUG.  Let me first refute some of the comments made and then
highlight points that make "C++ the HDL language of choice".  I've also
added a C++ up-down counter example to provide support to some of
my claims.  Let me further clarify that my comments regarding C++ HDL
language are derived from my experience with the CynApps library (Cynlib).

 
> "I agree with Geir," John Reynolds of Intel quickly replied, "Evaluate
> some of the tools and you will quickly see how restricted you are and the
> things you cannot model.  The observation that one engineer had around
> here when discussing the C/C++ vs. HDL argument was that the more you
> restrict C++ by using class templates, etc., the more you shave the
> language so that you can synthesize it, the more funky crap you add into
> the language to simulate concurrency already found in HDLs, the more your
> 'language' approaches a Verilog or VHDL!"

What is wrong with this?  CynApps provides a library of macros that
makes the language look very much like Verilog.  Designers, familiar with
Verilog, can learn to use the tool quickly.  New designers can leverage
old Verilog constructs as well as take advantage of powerful C++
constructs.  Designers can have the best of two worlds.


> I still think it's a dumb idea...  I was in a conference call yesterday
> with the folks from Synopsys talking about this "SystemC" stuff.  Some
> parts I like, but others are just too much trouble -- you'd might as well
> just learn VHDL or Verilog (so my theory is confirmed, once again :).
>
>     - John Reynolds
>       Intel

The problem with remarks like the one above is that they strictly focus
on the design effort.  Does anyone read white papers on ASIC design?
Today's ASIC design projects are bottlenecked by verification.  C++ is
the perfect language for verification.  In fact,  many groups already use
C++/Verilog co-simulation environments.  The problem is that this process
is slow because C++ communicates to Verilog through slow PLI, socket calls.


> They are creating a new language, Superlog, which is essentially an
> evolution of Verilog combined with C.
>
>     - Anders Nordstrom
>       Nortel Networks 

The problem with Superlog is that it's a new language.  Most designers
know C today.  Why not take advantage of a universal language like C++
and use it for both its ability to look like Verilog as well as its 
verification and design extensibility capabilities?

Here's a simple Cyn++ up-down counter example, used in a design contest
sponsored by you, John, in 1995, to show how C++ can resemble Verilog.

   Module up_down(In<1> clk,  In<1> up,  In<1> down, In<9> data_in, 
                  Out<1> parity_out, Out<1> carry_out, 
                  Out<1> borrow_out, Out<9> count_out) 

    Uint<10> cnt_up, cnt_dn; 
    Uint<9> count_nxt; 
    Uint<1> load;
                               
   Always( Posedge(clk) ) { 
      cnt_dn = count_out - 5; 
      cnt_up = count_out + 3; 
      load = 1; 

      switch( (up,down) ) { 
        case(0): 
            count_nxt = data_in; 
            break; 

        case(1): 
            count_nxt = cnt_dn; 
            break; 

        case(2): 
            count_nxt = cnt_up; 
            break; 
          
        case(3): 
            load = 0; 
            break; 
      }
                      
      if( load) { 
          parity_out <<= CynRedXor(count_nxt); 
          carry_out <<= up&cnt_up(9); 
          borrow_out <<= down&cnt_dn(9); 
          count_out <<= count_nxt; 
      } 
   }
   EndModule 


Now a summary of reasons why to use C++ has a HW design language:

  1) No new langauge to learn.  Most engineers already know how to
     program in C/C++.

  2) With the proper macro libraries, the language looks just like
     Verilog, making transisition from Verilog to C++ easy.

  3) One language for both design and verification.

  4) Simulation speed by eliminating the PLI bottleneck.

  5) Free simulations!!

  6) Simply, a well structured, powerful, mature language.

The only reasons that come to mind against C++ is the maturity level of the
synthesis tools as well as integration of C++ with other EDA  tools.  The
first is already being solved.  The second will evolve over time.

    - Bill Steinmetz
      Cisco Systems