( ESNUG 334 Item 5 ) --------------------------------------------- [10/28/99]
Subject: ( ESNUG 333 #6 ) Get DC Verilog Netlists Into Cadence Dracula LVS
> My company has its own fab and, unlike an ASIC buyer, after synthesizing
> a chip with Design Compiler and laying it out w/ our place-and-route tool,
> we use Dracula to run LVS. Now, Design Compiler writes out Verilog (not
> CDL/spice). LVS usually requires a CDL/Spice netlist (CDL is 99%
> identical to Spice):
>
> Design Compiler -> (Verilog netlist) -> Translator -> (CDL) -> Dracula
>
> For the past few years we've been using a Verilog2CDL/Spice translator
> from a vendor who is not fully committed to supporting and upgrading it.
> Our current solution has lots of problems and we're more than ready to
> find a better solution. Although many of our new products will use
> Avanti's Hercules instead of Dracula (Hercules readily accepts Verilog
> input), most of our projects will still use Dracula this year.
>
> Can anyone tell me either (1) how they get Design Compiler output into
> CDL/Spice, or (2) a different solution to this problem? Are there other
> Verilog2CDL/Spice translators available on the market?
>
> - Andy Frazer
> Integrated Device Technology Santa Clara, CA
>
From: Nir Sever <nir@gigapixel.com>
John,
Dracula supports Verilog (version 4.6 if I recall correctly). The flow is:
1. Run 'van' to analyze your Verilog netlist into a 5x format library.
2. Run LOGLVS
2.1 Use CIR commands to load your leaf cell's CDL/SPICE files
2.2 Use NVER to load your 5x library
2.3 Use CON to create the netlist (LVSLOGIC.DAT)
3. Run PDRACULA
4. Run jxrun.com
Make sure you have the latest Dracula release.
- Nir Sever
GigaPixel Corp. Santa Clara, CA
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From: "Joe Kryzak" <jkryz@rocketchips.com>
John,
We also use Dracula in our flow, and have seen success with direct Verilog
in, bypassing CDL. We've also used EDIF, but had to have a top level CDL,
which was a pain. I would recommend Verilog.
Actually the Verilog input works quite well at the "logic" level that
Cadence refers to. I believe you can't mix EDIF and Verilog however, at
the "logic" level. We are just in the process of a design that we will be
reading into Dracula, but it will contain not only verilog blocks, but
analog devices instantiated in Verilog. The primitives for these analog
blocks are, of course, in CDL. In the last week, we've read in a Verilog
I/O pad ring that contained standard cell IO's, multiple independent powers
and custom analog IO's. The powers were the tricky part, because we needed
VSST, VDDT, VDDD, VSSD, etc as opposed to VCC and GND.
So, my opinion is to blow off CDL altogether, unless your standard cell
primitives are in that format, or you have analog blocks like we do. Our
digital primitives are in spice, although it is almost the same as CDL.
But, for the gate level version of your digital portion, I would recommend
Verilog in at the "logic" level.
- Joe Kryzak
RocketChips, Inc. Minneapolis, MN
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