( ESNUG 333 Item 6 ) --------------------------------------------- [10/20/99]
From: Andrew Frazer <Andy.Frazer@idt.com>
Subject: Need Suggestions For Verilog-To-CDL Translators For Dracula LVS
Hi, John,
This question pertains to users who are doing their own synthesis and use
Cadence Dracula for post-layout LVS...
My company has its own fab and, unlike an ASIC customer, after synthesizing
a chip with Design Compiler and laying it out with our place-and-route tool,
we use Dracula to run LVS. Now, Design Compiler writes out Verilog (not
CDL/spice). LVS usually requires a CDL/Spice netlist (CDL is 99% identical
to Spice):
Design Compiler -> (Verilog netlist) -> Translator -> (CDL) -> Dracula
For the past few years we've been using a Verilog2CDL/Spice translator from
a vendor who is not fully committed to supporting and upgrading it. Our
current solution has lots of problems and we're more than ready to find a
better solution. Although many of our new products will use Avanti's
Hercules instead of Dracula (Hercules readily accepts Verilog input), most
of our projects will still use Dracula this year.
Can anyone tell me either (1) how they get Design Compiler output into
CDL/Spice, or (2) a different solution to this problem? Are there other
Verilog2CDL/Spice translators available on the market?
- Andy Frazer
Integrated Device Technology Santa Clara, CA
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