( ESNUG 263 Item 1 ) -------------------------------------------- [8/27/97]

Subject: (ESNUG 262 #4) Tell Me Names!  *WHO* Is Using Behavioral Compiler?

> "How come there were no papers on Behavioral Compiler at SNUG'97?  At the
> Applied Behavioral Compiler Tutorial (which was _excellent_ btw) they
> mentioned about 50 companies worldwide using BC.  Yet only one chip taped
> out so far! How can this be?  Do companies really spend $150K on a tool
> and then not use it?  Does it really reduce the time to market?"


From: [ Thinking Of Jumping ]

John, please have me be anon because I don't want my boss to know I'm
thinking of jumping.

Yes, there really _are_ companies that shell out the big bucks for BC
and not use it.  I interviewed recently at General Instrument, and the
manager was impressing on me the fact that they are one of the most
EDA-rich companies around.  They had loads of DC licenses, Test
Compiler licenses, simulation tools, and BC.  I was surprised, since I
had never personally met somebody who used BC, and asked how what
their results were with it.  The reply was "well, nobody has actually
done a design with it, but we have it"  Turns out that no designer was
comfortable compiling a design with BC since they felt they couldn't
really control the results.  Until that attitide changes, I doubt BC
will be a success.  Here, our company's attitude is, "well it looks
great, but for the price we'll wait and re-evaluate if it starts to
catch on in the industry."  It surely hasn't yet.

  - [ Thinking Of Jumping ]

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From: David Barda <davidb@vast.unsw.edu.au>

Dear John,

I do not believe the synopsys advertisements about the performance and
results of its behavioural compiler.

  - David Barda
    CAST laboratory
    University of New South Wales

         ----    ----    ----    ----    ----    ----   ----

From: "Victor Duvanenko" <victor_duvanenko@truevision.com>

John,

  I've been eye-ing Behavioral Compiler (BC) for the last 3 years, and
have just been through training on BC.  However, I'm still not convinced
that a clear productivity gain (or coding reliability improvement), as
there is with Design Compiler, which I've been happily using for the last
5 years.  This uncertaintly may just be due to the domain of my design
space.  Would any BC users share there experiences and thoughts of 
applicability of BC to their design domain?!  I have seen the David Black's
of Apple example in Synopsys's "Impact!" mailer, but would like to here
more specifically and in all of their goury technical details where BC
helped a user over RTL design methodology!  I would also love to see
positive and negative comments about BC.

  - Victor J. Duvanenko
    Truevision

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From: ANTONIO@atitech.ca (Antonio Asaro)

Hi John,

Help!!

I'd like to know what you think of BC (Synopsys's Behavioral Compiler).  Our
Synopsys rep has been touting the tool as the "wave of the future" - the
analogy being how language compilers reduced/eliminated the need for
low-level assembly language.  They've gotten all sorts of software-type guys
aroused who now think they can design hardware!!

  - Antonio Asaro
    Atitech

         ----    ----    ----    ----    ----    ----   ----

From: Dwayne Bennett <Dwayne.Bennett@Matrox.COM>

John,

Up until just recently I worked at HP. I used the BRT feature of Behavioral
Compiler on a design we called "OX" which was subsequently signed-off in
Nov/96.

My experience with BRT was very positive.  I had a circuit which needed an
extra stage, but adding this extra stage would have seriously affected
performance of the circuit and this could not be tolerated (the chip was
for a giga-bit Fibre Channel Switch and operated at 53Mhz.)  The solution
was to better make use of the stages I had by optimally placing them along
the critical path.  Unfortunately this path involved indexing into arrays
and so changing the placement of stages in verilog RTL would have been a
mess and would have been time-consuming.  This is when I turned to BC.  The
change to the synthesis script was trivial; I just added the command 
"optimize_registers" and let it run.  It resolved the problem and the
circuit was able to meet our timing goals.  The cost in gates was minimal.

I might add that a change to the verilog not only would have taken up my
time, but also would have forced a slew of regression simulations to have
to be re-run.  I think it is clear that BC/BRT saved me significant time
and effort.

  - Dwayne.Bennett
    Matrox



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