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\ - / INDUSTRY GADFLY: "My Cheesy Must See List for DAC 2017"
_] [_
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Here's my unofficial guide to the Austin DAC'17 exhibit floor. Enjoy!
CALIBRE, STAR-RC, & RIVALS
1.) Two months ago at CDNlive'17, Anirudh Devgan launched a surprise
attack on Joe Sawicki's Calibre DRC/LVS monopoly in ESNUG 571 #2.
NEW! -- Cadence Pegasus DRC "massively parallel DRC engine" runs
900 CPUs linear. 8X/12X faster. For Innovus PnR, does signoff DRC,
incrental DRCs, signoff metal fill, incremental metal fill, timing-
aware metal fill, and MPT decomposition for FinFETs. For Virtuoso,
Pegasus does on-the-fly DRC and metal fill work -- with NO memory
streaming; and dynamically does object creation/editing/deleting
feeback directly to the user. Uses olde factory certified Cadence
PVS decks -- no need to chase TSMC/GF/ICF/UMC for Pegasus decks.
LSF or Amazon AWS cloud, too. Texas Instruments & Microsemi users.
(booth 107) Ask for Manoj Chacko. Freebie: Denali party tix
Calibre nmDRC is the industry's DRC/LVS king with all 7nm tapeouts
today using Calibre for sign-off and they'redeveloping 5nm. It
scales to 2K CPUs for designs and 10K CPUs for manufacturing. It
competes vs. Synopsys IC Validator and Cadence PVS & PVSII/Pegasus.
TSMC, Samsung, GlobalFoundries, SMIC, UMC all use Calibre.
Calibre Pattern Matching replaces text-based design rules with visual
geometry capture and compare. It completes against Cadence Pattern
Analysis, Synopsys IC Validator, Anchor D2DB-PM. It kicks ass on
regular SRAM elements, and for curved structures like analog, RF, and
MEMS. Has Auto-Waivers for visual DRC checks to save time. Also
quickly locates & removes design patterns that are "yield detractors".
Aimed at 10/7/5nm designs. Now does Loop DFM/Compact PRISM for
the Samsung processes. Users are Samsung, GlobalFoundries, SMIC, UMC
(booth 947) Ask for Michael White. Freebie: K'Nex
Cadence Quantus QRC competes with Star-RCXT and Calibre-xACT. Does
multi-corner/statistical/inductance RLCK extraction, 16/14/10/7nm
Modeling, distributed processing, netlist reduction, SNA. Double
patterning, 3D-IC. 41 FinFET customers and 3 FD-SOI. Reliability.
Constraint validation. Works "in-design" in Innovus and Virtuoso.
(booth 107) Ask for Hitendra Divecha. Freebie: Denali party tix
Mentor Calibre-xACT does massively parallel full chip RLC parasitic
extraction without tiling. Processes entire net on a dedicated CPU.
No boundary and halo effects. "Attofarad accuracy with multi-million
instance digital or custom designs." Hybrid MOL/BEOL solver good to
7nm. Multi-patterning. Decks from TSMC, Samsung, GF available.
(booth 947) Ask for Carey Robertson. Freebie: K'Nex
Silvaco Belledonne compares layout versus layout, quickly finds the
differences with respect to wiring, and tells if diff is important.
(booth 1447) Ask for Jean-Pierre Goujon. Freebie: tote bag
Mentor Calibre DESIGNrev is a fast GDSII & OASIS viewer/editor with
tight with Calibre. "Filemerge" to merge layouts for chip assembly.
(booth 947) Ask for Joseph Davis. Freebie: K'Nex
Sage iDRM is a physical design rule compiler. It finds all places
in your physical design where your "test" rule applies -- plus where
it's been violated. It helps make sensible DRC decks. 22nm - 5nm.
(booth 513) Ask for Coby Zelnik. Freebie: pens
Mentor Calibre YieldEnhancer fills both low nodes and complex analog
blocks. Now has push button ECO Fill solution. Synopsys IC Validator
and Cadence PVS competitors. ("Cadence Pegasus fill is not supported
by any foundry.") TSMC, Samsung, GlobalFoundries, SMIC, UMC are users.
(booth 947) Ask for Jeff Wilson. Freebie: K'Nex.
Coventor SEMulator3D is a tool for the fabs themselves to simulate
the manufacturing process in 3-D. Virtual fabrication. To test
fab effects. It rivals Synopsys Sentaurus and Silvaco Victory.
Has new "Big Data" analytics. GlobalFoundries, Micron, IBM, Imec
NEW! -- Coventor MP creates finite element & reduced order models
for MEMS to go into MatLab, Simulink, Virtuoso, or Verilog-A SPICE.
(booth 239) Ask for David Fried. Freebie: none
PORTABLE STIMULUS
2.) A tipping point is coming. This week the PSWG just took a neutral
stance in the Breker C++ vs. Cadence/Mentor DSL language wars about
defining Portable Stimulus (PS) -- which promises UVM reuse from
HW all to way the final SW developers.
UVM Simulation ==> HW/SW Emulation ==> final post-Silicon
It's like the UVM vs. OVM wars, but with Portable Stimulus being
high level behavioral C BFMs/TLMs that run reeeeally 1000X fast.
Breker TrekSoC -- these are the grand daddies of PS, been doing it
since 2008. TrekSoC gens multi-threaded, multi-processor, multi-
memory C tests for cache coherency and uP-memory workload perf.
New power management app, ARMv8 app, and the tool is PSS compliant.
Verdi debug. Users Huawei, Broadcom, IBM, Nvidia, Altera/Intel.
Cavium used it for 3-chip 144 mixed cores in silicon bring-up lab.
(booth 1321) Ask for Adnan Hamid. Freebie: USB cellphone charger
NEW! -- Cadence Perspec is on the DSL side, it's a multi-core ARM
verification library/tool for cache coherency, distributed virtual
memory, low power. "We're swimming in ARM cores, John!!! Swimming!"
Qualcomm, Samsung, Mediatek, Renesas, ST, TI, Infineon are users.
(booth 107) Ask for Mike Stellfox. Freebie: Denali party tickets
Mentor Questa inFact is DSL that "achieves System Verilog coverage
25X faster than old school constrained random test." Generates SV
IP level tests & system level C/C++ tests. It can now import SV
constraints. Users are Applied Micro, Ciena, Microsoft, Microsemi.
(booth 947) Ask for Mark Olen. Freebie: K'Nex
SCOOP! -- Synopsys Mystery PS Tool is rumored to be coming out at
this DAC'17. Unknown if DSL or Breker C++ or something else...
Spies say it's to be roughly based on their Certess Certitude tool.
EMULATION / ACCELERATION / PROTOTYPING
3.) Palladium had a kickass 2016; but Veloce has a new Crystal3 chip.
Cadence Palladium Z1 has 23 use models incl. dynamic power analysis
with Joules, UPF/CPF, ICE in MHz, SpeedBriges, VirtualBridges for
SW months earlier, virtual debug interfaces, Xcelium sim acceleration
(RTL & Gates). Pairs with Cadence Protium for fast bring-up on FPGA.
Merges coverage from sim, acceleration and emulation runs. Virtual
& hybrid allow 60x faster SW bring-up, virtual verf. machine VVM for
offline debug for 100s of SW developers. Scales to 9.2B ASIC gates
for 2,304 simultaneous users in data center, water or air cooled.
5x better throughput. Do jobs virtually, dynamic job reallocation
for gets 2.5x better utilization. Cavium, Fujitsu, Huawei/HiSilicon,
MobileEye, Marvell, Mellanox, MicroSemi, NVIDIA, Renesas, Socionext.
CDNS ARM Suite optimized for ARM v7/v8, HW/SW co-design, debug, OS.
(booth 107) Ask Frank Schirrmeister. Freebie: Denali party tix
NEW! - Mentor Veloce Strato is the reigning king emulator with a
whopping 15 billion gates capacity from it's new Crystal3 chip.
(See ESNUG 567 #1 & 567 #3.) In the Veloce vs. Palladium seesaw,
it's always been the newest uP chip that wins the sales! CDNS
counters by saying: "we're not seeing Strato boxes anywhere..."
(booth 947). Ask for Jean-Marie Brunet. Freebie: K'Nex
Mentor Veloce 2 does 50+ MHz embedded SW execution with Warpcore and
Codelink. VirtuaLAB peripherals: 256-port Ethernet, PCIe Gen3, USB-3,
SATA, SAS, VJTAG. RTL-waveform debugger. Does ICE and Virtual.
Broadcom, Mitsubishi, NXP, ST, Trident, ZTE, HiSilicon use Veloce 2.
Mentor Veloce Apps. Has app tight with Ansys Apache PowerArtist.
It got RTL power reduction analysis 4.5X faster. Now there are 8
other Apps: Coverage, Assertion, Deterministic ICE, ICE, Power,
SW Debug, DFT, and last year's secret -- Ixia Virtual Network App.
(booth 947). Ask for Vijay Chobisa. Freebie: K'Nex
SCOOP! -- Synopsys EVE ZeBu-4 is to be secretly launched to a few
customers at DAC'17. Word is it was late being launched because
it's only 9 billion gates vs. Mentor's new 15 billion gate Strato.
TLMs, power-aware, sim acceleration, ICE, synthesizable testbench.
(booth 147) Ask for Tom Borgstrom. Freebie: pens
ProDesign proFPGA is like SNPS HAPS but based in Germany. Mix match
Xilinx Virtex 7 330T to 2000T to Altera Stratix 10. 600 M ASIC gates.
13.1 Gbps. In 3 years ProDesign shipped 751 units to 61 customers.
(booth 1632) Ask for Gunnar Scholl. Freebie: pens
S2C Prodigy Player Pro 6.4 is like HAPS but from a start-up. Virtex
and Kintex UltraScale. Multi-board partioning. Pin multiplexing up
to 1.6GHz LVDS. Quad, dual, single modules. Cable after partition.
NEW! -- Prodigy Multi-Debug Module is like Synopsys Identify debug.
NEW! -- Prodigy A10 Logic Module based on Intel Arria 10 GX1150 FPGA.
"to prototype small to medium sized SoCs" Can scale to 16 modules.
(booth 739) Ask for Richard Chang. Freebie: pens
Aldec HES-7 uses UltraScale U440's. Claims 633 M gates. Auto
partitioning, ASIC-to-FPGA clock conversion, static/dynamic probes,
memory viewer, HW breakpoints. Ethernet, USB, USB-OTG, HDMI, I2C,
SPI, RS232, GPIO, ARM Debug & JTAG. Qualcomm, Samsung, Fuji-Xerox.
NEW! -- HES-DVM Cloud now does does System Verilog DPI-C TLM's,
virtual SW, and ICE in the Amazon AWS EC2 cloud.
Aldec TySOM Ty-1 is a system-on-module development board of
a Xilinx Zynq XC7Z030, memories (512MB DDR3, uSD), communication
(Ethernet, USB, Pmod, JTAG) and multimedia. Reference designs and
Linux ports. For IoT, ARM, automotive, UAV/UAS, home automation.
(booth 421) Ask for Christina Toole. Freebie: texas longhorn dolls
Dini Group DNVUF4A -- ASIC prototype 4 Virtex UltraScale XCVU440's,
each with capacity of 116 million ASIC gates. Seamless stack 8 or
more of these boards to prototype 1 billion ASIC gates. 2,892 BGA.
16 GbE with no external Phy needed. GEN3 PCIe, SATA III, USB 3.0.
Dini Group DN_ReadBacker lets you read back the complete status
of your FPGA registers for debug. "No one else does this, John!!!"
(booth 1723) Ask for Mike Dini. Freebie: grumpy Mike sayings
NEW! -- Cadence Protium-S1 homebrew FPGA-based prototyper. Lip-bu's
answer to SNPS HAPS. Auto ASIC-to-FPGA memory conversion, automatic
clock synchronization to avoid hold-time violations and FPGA-specific
limitations, pre-P&R model validation. "quick bring up in 1-2 weeks
instead of 3-4 months." SCE-MI based transaction interface, memory
backdoors, start-stop-clock control and scripting for SW developers.
Nvidia, Mellanox, Microsemi, Marvell, Sony, NXP, Medtronic, Xilinx.
(booth 107) Ask for Juergen Jaeger. Freebie: Denali party tix
Synopsys HAPS-80 and ProtoCompiler claims 1.6 billion ASIC gates
at 100 Mhz speeds from 64 total Xilinx Virtex UltraScale VU440's.
(booth 147) Ask for Joachim Kunkel. Freebie: pens
IR-DROP / NOISE / THERMAL / POWER
4.) Ansys Gear SeaHawk is John Lee's R&D guys bringing those much talked
about Big Data into the RedHawk IR-drop/EM franchise. (ESNUG 554 #1)
It doesn't change RedHawk itself -- SeaHawk guides RedHawk for best
QoR. Claims are SeaHawk can reduce die size by 5%. The gotcha is
SeaHawk/RedHawk is getting inconsistant results. (ESNUG 563 #10)
(booth 647) Ask for John "Jolly" Lee. Freebie: stuffed bulldog
Ansys Apache RedHawk is full-chip/3d-IC power integrity analysis and
sign-off, transients, simultaneous switching noise package/PCB with
distributed processing. Scalable to 16-32 machines (128-256 cores).
"500M insts with 8B resistors while keeping flat simulation accuracy"
Vector-based and vectorless. Clock jitter. TSMC 16/10/7nm FinFET.
NEW! -- RedHawk-SC claims "IR-drop in 6 hours on a 1 billion gate
chip on a 16G machine" and "does 1000 scenarios overnight". Says
its 2 years old, so it's a rebranding of earlier SeaHawk/SeaScape.
Maybe they fixed the inconsistency/accuracy problems now?
Their Pathfinder ESD does full-chip multi-domain, multipath electro-
static discharge analysis. Capacity 8B transistors with critical
path tracing to identify and fix stressed device junctions. Their
Totem is transistor power-noise-reliability analysis. 16/14/10/7nm.
Apache users Samsung, NXP, ST, Applied Micro, Nvidia, Avago, AMD.
(booth 647) Ask for Arvind Vel. Freebie: stuffed bulldog
Cadence Voltus-DP is Lip-bu's attack on Apache/Ansys RedHawk. Does
full-chip signoff, IR-drop, Power-Grid-Views. Massively parallel.
1B insts over 100s of compute CPUs. It won two user benchmarks
against RedHawk in ESNUG 560 #3 and ESNUG 561 #1. Now does ECO's.
Works with Tempus and Sigrity chip/package/board and Innovus PnR.
Early Voltus user cut runtime 9 days to 1 day on a large ARM design.
Now in TSMC 7nm ref flow. HiSilicon, Juniper, TI, ARM, Nvidia, NXP,
TSMC, GF, Samsung, STM, ON Semi, Spreadtrum, Mellanox, Renesas, ADI.
Voltus-Fi does transistor-level noise/power signoff with Quantus QRC
and MMSIM inside Virtuoso. Both Voltus & Voltus-Fi are TSMC 10/7nm.
Apache Totem and Synopsys HSim-PWRA both compete against Voltus-Fi.
(booth 107) Ask for Jerry Zhao. Freebie: Denali party tickets
Silvaco InVar does super quick IR checks on FinFETs using only your
layout data. Snoops out high IR-drop, high current density related
EM issues, etc. Does "point-to-point interactive resistance checks,
pin resistance mapping, and very fast What-If analysis iterations."
Competes against Ansys Totem and Cadence Voltus. Toshiba uses InVar.
(booth 1447) Ask for Alex Samoylov. Freebie: black bear doll
Teklatech FloorDirector does pre-CTS power integrity analysis for
lowest on-chip dynamic voltage drop. Then it fixes the problem.
Sparcer pwd grid, faster performance, and lower area. 10/7nm
(booth 441) Ask for Tobias Bjerregaard. Freebie: Viking hugs
Magwel ESDi also does ESD analysis just like Apache Pathfinder ESD.
Checks all possible shunt paths during event; fewer false positives.
It can now handle chips as big as 10x10 mm^2 on up to 1000 pins.
NEW! -- Magwel PTM-TR uses a 3D field solver to do fast-but-accurate
transient Spectre simulation of power transistor circuits. Used for
switching power loss, check current crowding, device reliability.
(booth 813) Ask for Dundar Dumlugol. Freebie: none
Silicon Frontline ESRA also does ESD analysis like Apache Pathfinder.
(booth 1015) Ask for Yuri Feinberg. Freebie: none
Entasys Navis optimizes pre-RTL number and location of power pads to
meet your target IR-drop and SSO noise margins. Samsung, LG users.
(booth 1829) Ask for DongJin Shin. Freebie: pens
DIGITAL P&R
5.) My true #5 "Must See" is about a person, and not an EDA tool.
Synopsys IC Compiler II -- it's been a trainwreck and career-killer
ever since it's March 2014 launch. (ESNUG 537 #10, 538 #1, 547 #7,
548 #1, 550 #1, 552 #6, 554 #3) Then on camera in ESNUG 563 #6:
"So what do I think of IC Compiler II? I think Antun
doesn't sleep well."
- Jim Hogan, DAC'16 Troublemakers Panel
Then 5 months later in late November 2016, Antun Domic, who's been
Mr. SNPS PnR R&D for decades is replaced by Sassine Ghazi, the VP
of North American Sales??? WTF? Then Jan/Feb 2017, I hear rumors
about a good number of 20-year SNPS R&D veterans being laid off???
So my #5 "Must See" is to see this Sassine guy to hear how he'll
fix, or not fix, what got Antun "promoted" to CTO, and out of R&D.
(booth 147) Ask for Sassine Ghazi. Freebie: pens
Cadence Innovus -- 27 months ago was Anirudh's attack on ICC/ICC2.
This DAC, I suspect Anirudh is going to rehash what he said 2 months
ago at CDNlive'17 in his 32 jabs at ICC/ICC2. (ESNUG 571 #3) His new
Innovus 17.1 has a 3x speedup (from 1.5X single-machine, and 2X with
new distributed processing) able to digest 7M instance block sizes.
Innovus + Voltus did ECOs with 93% less victims. (DAC'16 #7) And
then he'll brag how Qualcomm, Nvidia, ST, Faraday, GF, HiSilicon, ARM,
Broadcom, Toshiba, Freescale, Juniper, Renesas, Maxlinear, Spreadtrum,
Silicon Labs, AltaSens, Cypress, ImgTec, NXP are all Innovus users.
I'm sure by now Aart regrets letting Anirudh go after the LAVA buyout.
(booth 107) Ask for KT Moore. Freebie: Denali party tickets
Mentor Nitro-SoC and Oasys-RTL -- are Wally's answer to Aart and
Anirudh in digital implementation. Oasys-RTL does crazy fast RTL
synthesis floorplanning, design partitioning, congestion analysis and
pre-CTS opto. 3 hours to synth & floorplan a 2 million inst chip
using 4G of machine memory. Can do 6 M inst flat. (ESNUG 560 #6)
Synthesized and floorplanned 14nm 3M inst chip in 8 hours and 3.8M
28nm design in 12 hours. Logical/physical/timing views in cockpit.
This year Nitro-SoC is tighter with Tanner/Pyxis/Virtuoso analog flows
to target digital-analog chips. It's dynamic area recovery and FinFET
power optimization gets 10% better area and power. Supports 7nm, and
direct hooks with Calibre signoff, simplified reference flows, etc.
ST, Samsung, Nvidia, MediaTek, ImgTec, GF, eSilicon, Onsemi, Ostendo
(booth 947) Ask for Arvind Narayanan. Freebie: K'Nex
And Atoptech filed for Chapter 11 bankruptcy on Jan 13th, 2017.
SPICE / AMS / CHARACTERIZATION
6.) MENT BDA AFS was 5x-10x faster vs CDNS Spectre in ESNUG 495 #4 and 2x
faster than SNPS FineSim Pro in ESNUG 535 #3. 20+ M elements.
Now TSMC 7nm certified. BDA ACE fully replaces Virtuoso ADE-XL for
analog characterization runs. AFS Mega does SPICE of 100+ M element
mega arrays like memories. It does DC, transient, transient with
dynamic temp, alters, sweeps, Monte Carlo. TSMC uses AFS Mega for
all 10nm SRAMs. Samsung, MediaTek, Intel, Broadcom, Qualcomm, NXP,
Fujitsu, ADI, Sony, LG, Magnachip, Panasonic, Skyworks are users.
(booth 947) Ask for Giuseppe Oliva. Freebie: K'Nex
Cadence Spectre-XPS is Lip-bu's comeback FastSPICE tool for memories.
Benchmarked 3-4X faster throughput than SNPS HSPICE in ESNUG 547 #3.
Has clever fast-or-accurate partitioning based on need. Multi-core.
(booth 107) Ask for Joy Han. Freebie: Denali party tickets
Silvaco SmartSpice Pro is Dutton's push into the memory
fastSPICE market. Claims "true SPICE behavior but with much faster
generation of waveforms" and "2X speed-up on AMOLED panel and SRAM
designs with better waveform overlay results than other simulators."
Does 28/16/14/10/7nm. SmartSpice (golden), SmartSpice HPP (parallel).
Samsung, LG, Oracle use it. SmartSpice PRO for SRAM simulation.
(booth 1447) Ask for Colin Shaw. Freebie: tote bag
NEW! -- ICScape ALPS claims "on average 2-5X speedup over the 3 other
true SPICE simulators" which I guess are MENT BDA AFS, Spectre APS,
HSPICE. 3 million transistors and 30 million RCs. (ESNUG 572 #6)
HiSilicon, Kilopass, Monolithic Power Systems, Ricoh, Toshiba
(booth 1433) Ask for Jason Xing. Freebie: fidget spinner
ProPlus NanoSpice Giga big ass capacity parallel SPICE. Did 576 M
element full-chip DRAM, 50.5 M transistor SRAM and 67 M element post-
layout SRAM. Does 1+ B elements for 16/14/10/7nm FinFET or 28nm
FD-SOI. 10X faster vs. parallel SPICE. Dolphin, OmniVision, eSilicon
(booth 1413) Ask for Lianfeng Yang. Freebie: cell phone clip
NEW! -- Solido ML Characterization Predictor uses machine learning
to cut characterization time by 30-70% (ESNUG 573 #4) by generating
Liberty models at new conditions from prior Liberty data at different
PVT conditions, Vt families, supplies, channel lengths, model revs.
It works with NLDM, CCS, CCSN, waveforms, ECSM, AOCV, LVF.
NEW! -- Solido Statistical Characterizer provides 3-sigma statistical
timing (LVF/AOCV/POCV) data with Monte Carlo and SPICE accuracy.
Is non-Gaussian, in under 1000X fewer simulations than brute force.
(booth 1113) Ask for Amit Gupta. Freebie: VR Demo
ProPlus ME-Pro lets you benchmark fab processes and devices.
Compare multiple foundries/multi-processes down to 7nm. No scripts
nor SPICE licenses needed to do 100's of comparisons! Qualcomm
(booth 1413) Ask for Lianfeng Yang. Freebie: cell phone clip
Silvaco Jivaro does netlist reduction for SPICE sim acceleration.
Multithreaded for DSPF/SPF netlists Speeds up Spectre by 3X. More
accuracy. OA DM5 is now supported. Silvaco Viso does quick analysis
of interconnect parasitics. Tight with Virtuoso. Silvaco Belledonne
does extracted netlist comparison -- for PDK optimization.
(booth 1447) Ask for Jean-Pierre Goujon. Freebie: tote bag
NEW! -- Entasys PathInspector builds sub-circuits automatically for
detailed analysis when full chip transistor-level analysis has a long
simulation time. Drag-and-drop to build a sub-circuit. SK hynix
(booth 1829) Ask for DongJin Shin. Freebie: pens
Solido Variation Designer does variation-aware design for PVT corners,
3 to 7-sigma Monte Carlo, hierarchical and sensitivity. Big thing
is it cuts waaaaaaay down on how many SPICE runs you need. Demoing
new 4.0 release with new GUI and CLI for memory, std cell, analog/RF,
custom digital. TSMC, Broadcom, Nvidia, Huawei, Cypress, ARM, IBM
(booth 1113) Ask for Amit Gupta. Freebie: VR Demo
MunEDA WiCkeD analyzes SRAM cell/column/array, std cell, and analog
circuits for local variation to 9-sigma. Hierarchical and WCA.
FinFET, Bulk, Bipolar, BiCMOS. ST Micro and MunEDA published
silicon & bit cell analysis of 14nm FDSOI statistical BTI effects.
Samsung, SK Hynix, Infineon, Sanyo, Toshiba, and Altera users.
(booth 1012) Ask for Andreas Ripp. Freebie: tote bags
ProPlus NanoYield is variation analysis on yield vs. PPA trade-off.
It does High Sigma Monte Carlo. Licensed from IBM eight years ago.
Can handle 10,000+ variables and does up to 7-sigma. Used by SMIC.
(booth 1219) Ask for Lianfeng Yang. Freebie: cell phone clip
Silvaco Variation Manager is the old Infiniscale IClys which does
Monte Carlo to 50X, and High-Sigma analysis 1,000,000X to 8 sigma.
Supports non-Gaussian. Batch mode library verification, too. They
also have Library Variation Manager that does characteration of 100's
of cells for you. For example, 28nm FDSOI, 40 cells, 100 corners,
Monte Carlo at each corner, 100's of measures, took 173 mins using
brute force MC and only 19 mins on Library Variation Manager.
ST Micro, Faraday, and Dolphin Integration uses these Silvaco tools.
(booth 1447) Ask for Prashant Singh. Freebie: ear buds
NEW! -- ICScape ICExplorer-XTime uses Big Data analysis to do much
faster & accurate Monte Carlo silicon timing sign-off. Does critical
path, sensitivity, and low power analysis. Design margin recovery.
(booth 1433) Ask for Jason Xing. Freebie: fidget spinners
Cadence Virtuoso Liberate LV/MX/Variety is rename of Altos cell lib
characterizer. Does electrical cell views for timing (NLDM), power
(NLPM) and signal integrity. CCS, ECSM, CCSN, ECSMN, AOCV/SOCV/LVF.
Likes Spectre APS. Rivals Liberty NCX, SiliconSmart, Mentor Kronos.
(booth 107) Ask for Hany Elhak. Freebie: Denali party tix
Integrand EMX is a 3D EM simulator for modeling on-chip passives and
interconnect and RF. Black boxing models active circuitry. Now
simulating full VCOs. Samsung, Broadcom, Nvida, MediaTek, TSMC, UMC.
(booth 1339) Ask for Sharad Kapur. Freebie: stress doll
Helic Exalto does 3D electro-magnetic (EM) crosstalk analysis and
signoff. Has killer capacity/speed/accuracy. 12Ghz chip with EM
coupling through PWR/GND. 2.8mm X 700u, with AP, M12-M7. Extracted
in 36 hours on 20 cores. Another SOC with EM crosstalk between multi
VCOs. Modeled seal-ring & bump pads necessary to analyze 20x15mm from
AP+M12 to M6. Full RLCK extraction in 24 hours w 350GB on 40 cores.
Rivals HFSS, Quantus. Users Huawei, NXP, Nvidia, AMD, Qualcomm.
(booth 341) Ask Yorgos Koutsoyiannopoulos. Freebies: squeeze ball
NEW SCHOOL RTL SIMULATORS
7.) Cadence Xcelium (Rocketick RocketSim) is parallelized System Verilog
across 100's of Intel CPUs. Benched 23X faster vs. VCS, Incisive,
Questa. Does gate and RTL sims. Compiles 1 B gates in 2 hours.
Does 4-state-logic for X. Full System Verilog and accelerates SVAs.
Xcelium got #3 User's Best of DAC'16 last year. (DAC'16 #3)
"This is the industry's first *working* 3rd gen simulator, baby!"
Customers Intel & Nvidia. HPE talking about migrating to Xcelium.
ARM sees 5X speed-up for RTL/gate; STmicro at 8X for DFT simulation.
(booth 107) Ask for Uri Tal. Freebie: Denali party tix
WHO TO BELIEVE?: Aart talks about his Synopsys Cheetah VCS as if it's
his own Rocketick-like simulator -- but my CDNS sources say: "Ask Aart
to name specific Cheetah VCS users. He can't. He's just messing with
our Xcelium sales with roadmap talk." Who should I believe???!!
(booth 147) Ask for Manoj Gandhi. Freebie: pens
BUGHUNTERS
8.) Cadence JasperGold has 14 formal Apps now. New this year that
they are showing at DAC'17 are: Superlint, RTL Signoff, and CDC.
"... full range of lint, DFT, formal checks, plus CDC and RDC..."
Samsung, Huawei, Nvidia, Qualcomm, TI, Broadcom, Marvell, Sony, ST.
(booth 107) Ask for Pete Hardee. Freebie: Denali party tickets
OneSpin 360 Verify does full-blown property checking combined with
coverage which "checks the checks" to direct assertions at uncovered
areas. Beats regular sim stimulus coverage. 360-SystemC allows SVA
assertions on C++ and SystemC, does X-state and race conditions.
360-Quantify does a full formal coverage of your code and SVAs.
Their 360-Safety injects faults into device code to see if it
recovers from an operational fault in the field, and still works.
Their 360 DV Inspect combines linting with property checking, user
doesn't have to write any assertions! Their 360 EC-FPGA does
equivalency checking RTL vs. post-synthesis netlists for FPGA's.
Renesas, Nokia, Infineon, Xilinx, Western Digital, Bosch, Maxsim.
(booth 1547) Ask for Raik Brinkmann. Freebie: fidget cubes?
Mentor Questa Formal has 11 formal Apps now. X-checking, RTL checks,
coverage, assertion checks, property generation, connectivity checks,
post-Silicon, register checks, CDC -- plus their SLEC now supports
safety-critical designs. New GUI with web and mobile clients.
Samsung, Cypress, Microsoft, Microsemi, Mediatek, AMD, and Oracle.
(booth 947) Ask for Joe Hupcey. Freebie: K'Nex
Synopsys Atrenta Spyglass plays heavily in killer linters, but I
don't know if they got space in the Synopsys booth this year.
Amiq Verissimo is like a Spyglass linter just for SystemVerilog
testbench code. Samsung, Cisco, Qualcomm, Xilinx, Toshiba.
(booth 1731) Ask for Cristian Amitroaie. Freebie: horseshoes?
Blue Pearl VV Suite lets FPGA engineers visually verify by way of
graphical FSMs, CDC and false path viewers with cross probing to RTL,
with forward and reverse tracing, and linting message filtering.
Raytheon, GE, Harris, BAE, Parker Hannifin, Lockheed, L3, IT Dev
(booth 1120) Ask for Ellis Smith. Freebie: water bottles
Real Intent Meridian CDC does new transparent hierarchical models
for separate CDC analyses at unit-level. New consistency checks
across chip hierarchy. On 300M gate chip with 103 clock domains,
the hierarchical CDC runtime cut by 5X and memory use cut by 4X.
(booth 928) Ask Vikas Sachdeva. Freebie: cellphone batteries
NEW! -- Real Intent Verix Multimode CDC is a "brand new tool for
true multi-mode CDC RTL analysis." Single set-up. All modes in
single run, no iterations. New static intent verification finds
non-operational clock modes. Vs. Spyglass or Questa, it saves 3.3x
CPU time and 5x engineering time per iteration. See ESNUG 574 #2.
(booth 928) Ask Vikas Sachdeva. Freebie: cellphone batteries
Ausdia Timevision-CDC does block/fullchip CDC analysis on RTL or
gates using SDC constraints only -- so it can verify your actual
clock groups as being CDC-safe. 500 M inst with 1000 clocks in
8 hours. GUI user does full tracing. Handles flop duplication,
retiming and merging. Qualcomm, Nvidia, Broadcom, Mediatek, ARM
(booth 1313) Ask for Sam Appleton. Freebie: fidget spinner
Excellicon ConDor does CDC claiming "NO setup, fastest run times
on 500M+ insts, flat. Only RTL or netlist input for multi-mode
hierarchical analysis." (booth 546) Ask Himanshu Bhatnagar.
Mentor Questa CDC "fast CDC, highest QoR." ISO 26262 certified.
new gate-level stuff for FPGAs. Mediatek, Continental, AMD, HP.
(Booth 947). Ask for Mark Olen. Freebie: K'Nex.
NEW! -- Cadence JasperGold CDC vaguely does all the whizbang stuff
competing CDC rivals do I guess... (booth 107) Ask Pete Hardee
Aldec ALINT does CDC rule checking. Viewer shows violating code.
(booth 421) Ask Christina Toole. Freebie: plush longhorn steers
Excellicon ConCert-ET verifies timing intent & structural exceptions
using SVA+/formal. ConCert does SDC, CTS, demotion, equiv checking.
ConMan formally crafts hierarchical constraints for multi/merged mode
SDC, promotion, clocking analysis. 500+ M inst. Users are LG,
Marvell, Renesas, Qualcomm, Western Digital, Maxim, ST, Socionext
NEW! -- ConCert-Physical does timing budgeting across partitions.
(booth 546) Ask for Himanshu Bhatnagar. Freebie: beer hats
FishTail Confirm now verifies if asynchronous resets are glitch safe
and reset domain crossings using formal and AVB. Requires no added
input - just SDC & RTL. SDC equivalence verifies if constraints are
correctly moved up/down design hierarchy. 40M gate design in 7 hrs.
Generation ofstop-clock propagation constraints cuts P&R runtimes by
3x with no impact on QoR. Mediatek, TI, Qualcomm, Xilinx, Cypress.
(booth 821) Ask for Ajay Daga. Freebie: none
Real Intent Meridian Constraints does SDC generation, validation and
multi-cycle path verification; New functional analysis of MCPs and
constraints exception verification removes need for formal analysis.
Gives 50% faster sign-off. Constraints promotion from block-level
to top-level. Has iDebug for database-driven smart reporting.
(booth 928) Ask Vikas Sachdeva. Freebie: cellphone batteries
Arcadia Innovation TimeHawk Constraints finds SDC patches
that used to be found during placement and CTS iterations. Saves
3 to 4 weeks of design iterations. Also does full chip SDC debug.
Claims 10+ million inst designs are "run in a couple of minutes."
(booth 915) Ask for Joey Lin. Freebie: pens
Real Intent Ascent XV does X-propagation checks. Ranks X-sources
and X-sensitive nets by failure importance. Initialization audits.
Setup-free X-pessimism analysis at gate-level with only 3X overhead
versus 5x-10X from other tools. Now goes deeper; found a gate-level
Xs in a 220M gate design. Replaces using VCS/Incisive/Questa's
X-safe simulation switches. Finds minimally correct reset schemes.
(booth 928) Ask Lisa Piper. Freebie: cellphone batteries
NEW! -- Real Intent Meridian RDC finds reset configurations and
complex reset interactions, not covered by existing tools. Finds
reset metastability and glitch problems. Optimized data models.
200M gate full chip RDC analysis in 9 hrs with ~160 G memory.
(booth 928) Ask Oren Katzir. Freebie: cellphone batteries
Avery SimXACT automatically find X bugs in RTL and eliminates false
X's in gate-level simulation. Has gated clock X pessimism analysis
and auto generated fix deposits. Verdi App to graphically view
force/release fixes as well as any real X backtrace logic cones.
(booth 229) Ask for Chris Browy. Freebie: cellphone mount
Cadence Conformal LEC does both gates-gates and RTL-gate logical
equivalence checking. The #1 selling LEC in Synopsys design flows
because it's wise to have a checker from outside your flow. Now
has multi-machine, multi-CPU parallelization and "first-time-right"
adaptive proofs make it 8X faster this year. Also regressible.
Intel, Xilinx, Broadcom, LG, Qualcomm, ARM, Samsung, NXP, HiSilicon
(booth 107) Ask for Avinash Palepu. Freebie: Denali party tickets
Mentor Visualizer Debug is Wally's debug answer to Cadence SimVision
Debug Analyzer and Synopsys DVE/Verdi. Visualizer debugs RTL, gates
and testbenches, automatic tracing to "pinpoint cause of errors".
(booth 947) Ask for Mark Olen. Freebie: K'Nex
NEW! -- Austemper FST is a functional safety tool. Vague write-up.
(booth 1420) Ask for Arun Gogineni. Freebie: none
Cadence Indago is Lip-Bu's answer to Aart's Verdi3 empire. Indago
debug works by adding Big Data Capture to Root Cause Analysis -- in
order to data mine your CDNS tool run logs -- to "highlight causality"
and correlations causing your bug in the first place. Does HW/SW bug
hunting. This year the Indago guys are hyping power-aware debug.
Analog Devices, IT, Bosch, Broadcom, Renesas, Siemens, ST, and Toshiba
(booth 107) Ask Larry Melling. Freebie: Denali tix
SystemC/C/C++/TLM STUFF
9.) Badru, Man with a Vision -- he's the MENT Calypto guy who's making
all that noise about his "C-based design Vision". (ESNUG 572 #5)
Mentor Catapult HLS 10.1 synthesizes C++/SystemC into Verilog/VHDL
to target either FPGA or ASIC. Kicks ass at developing designs for
accelerating machine vision and machine learning. Supports top-down
and bottom up, cuts project times at least in half and verification
costs by 80%. Snappy new Visualizer design analysis shows C->RTL,
plus new libraries for FPGA (Xilinx and Altera) to crank the clock
and hooks into Mentor Oasys-RTL.
NEW! -- Mentor Catapult DesignChecks does formal checks on SystemC
and ANSI C++. This competes against the OneSpin 360-SystemC tool.
It auto checks array overflow, underflows, uninitialized variables,
divide-by-zero, array bound errors, illegal shifts. Proves user
assertions & cover points. Generates test vectors for reachable code.
Qualcomm, Nvidia, ST, Google, Thales, Ericsson, Fujitsu, Toshiba.
(booth 947) Ask for Badru Agarwala. Freebie: K'Nex
Cadence Stratus HLS takes in untimed SystemC/C/C++ to generate Verilog
RTL that Design Compiler or CDNS Genus can easily digest. Can do both
control logic and datapaths. Claims better accuracy than Catapult.
Hooks into CDNS Genus RTL synth, Joules low power, and Innovus PnR.
Supposedly can see PnR congestion issues in your SystemC/C/C++ source.
HiSilicon, NXP, Bosch, Samsung, LG, Realtek, Toshiba, Fujitsu, Ricoh
(booth 107) Ask for Brett Cline. Freebie: Denali party tix
NEC CyberWorkBench -- these Japan guys have been doing C/C++/SystemC
to Verilog/VHDL RTL synthesis since the beginning of time. This year
they have an ARM bus I/F generator, Memory Mapped Register generator.
Mitsubishi, Renesas, Panasonic, Toshiba, Hitachi, Fujitsu, JVC users.
(booth 1520) Ask for Kazutoshi Wakabayashi. Freebie: magic puzzle
Synopsys Synphony C plays here but probably not showing at this DAC.
Calypto SLEC does SystemC/C++/C-to-RTL functional equivalence. Tight
EC with Catapult; less tight vs. SNPS Synphony or CDNS Stratus. Also
C++ assertion/property checks. Rivals Synopsys Hector and Jasper EC.
Runs "bottom up" partitions. New LSF support. Google, ARM users
(booth 947) Ask for Badru Agarawala. Freebie: K'Nex
Fraunhofer COSIDE is a system level tool based on SystemC as well
as on SystemC AMS 2.0. Competes vs. Matlab Simulink or MENT Vista.
(booth 339) Ask for Karsten Einwich. Freebie: cookies
Imperas does virtual platform based software development, debug and
test. Acceleration on multicore hosts. It competes against Cadence
Virtual, Synopsys Virtualizer, Mentor Vista, and Wind River Simics.
NoCs. Fault injection. Linux, FreeRTOS, OpenRTOS, uC/OS, MQX, eCoS.
Now Imperas OVP has 40 EPKs, 170 CPU models of ARM, MIPS, RISC-V.
Users are ImgTec, Renesas, Recore, Altera, Audi, AMD, Nagravision.
(booth 521) Ask for Larry Lapides. Freebie: coasters
VERIFICATION IP
10.) Mentor Questa Verification IP (VIP) is a big ass library of UVM VIP.
- AMBA Family (CHI 5, ACE 4, ACE-Lite, AXI4, AXI3, AHB, APB);
PCIe Family (PCIE 4.0, PCIe 3.0, PCIe 2.0, PCIe 1.1, PIPE, PIE-8,
SR-IOV, MR-IOV, NVMe, AHCI); USB Family (USB 3.1, USB 3.0+OTG,
USB PD, PIPE, xHCI, SSIC, USB 2.0+OTG, UTMI+, UTMI, ULPI, oHCI,
eHCI); Ethernet (400G, 100G, 50G, 40G, 25G, 10G, 1G, 100M, 10M,
PTP, MDIO, EEE, MII, RMII, GMII, TBI, RTBI, SGMII, RGMII, QSGMII,
BASE-X, BASE-T, BASE-R, BASE-W, CAUI, XGMII, XAUI, XLAUI, RXAUI,
HI-MoM, XSBI, XLGMII, CGMII, HiGig2, FEC, Auto-Neg); Serial Family
(SmartCard, SPI-TI, SPI-Moto, SPI-NS, SPI 4.2, UART, I3C, I2C 5.0,
I2S-Philips, I2S-TI, JTAG); MIPI Family (MPHY 3.0, LLI 2.0,
DSI 1.1, CSI-3, CSI-2, DigRFv4 1.2, HSI 1.0.1, Unipro 1.6,
UFS 2.0); DDR Family (LPDDR4, LPDDR3, LPDDR2, DDR4, DDR3, DDR2,
DFI 3.1, Wide IO 2, DRAM Model Generator); FLASH Family (SDCard4.2,
SDIO4.1, eMMc5.1, ONFI4.0, Toggle, UFS, Parallel NOR, Serial NOR);
Display (CDC, DisplayPort, eDP, V-by-One, HDMI 2.1, HDMI 2.0,
HDMI 1.4, HDCP 1.4); HyperBus (Hyperram, Hyperflash); Auto (CAN,
CAN-FD, LIN); Mil-Aero (Spacewire, 1553b, PCI); 5G (JESD204B,
CPRI); Storage Family (SATA); NVMe over Fabric, Interlaken, I3C.
Each protocol comes with a testplan, functional coverage, assertions,
examples and stimulus. ARM, Cypress, Microsemi, Marvell, ST users.
(booth 947) Ask for Mark Olen. Freebie: K'Nex
Cadence Verification IP (VIP) is a mix of Verisity Specman "e" VIP
plus the Denali VIP plus homegrown CDNS VIP from consulting gigs.
- have VIP for "AMBA 5 CHI, eMMC 5.0, HDMI 2.0, LPDDR4, MIPI C-PHY,
MIPI CSI-3, MIPI SoundWire, Mobile PCI Express, PCI Express Gen 4,
USB SuperSpeed Inter-Chip, Wide I/O 2, Ethernet 25G/50G, HBM, HMC,
MIPI DSI-2, WiFi MAC" -- plus new "CCIX, BLE5, DDR5"
Denali-style API, all simulated VIP runs on VCS, Questa and Incisive.
"VCS or Questa customers do not need Specman e". TripleCheck.
Broadcom, HP, IBM, Intel, LSI, Hitachi, Marvell, Qualcomm, Samsung.
Rumor is CDNS PCIe 4.0 passes certification, while Synopsys doesn't.
(booth 107) Ask Moshik Rubin. Freebie: Denali party tix
Avery Verification IP (VIP) for PCIe Gen4, DDR4 LRDIMM/RCD2/DB2 and
3DS, MIPI CSI and DSI for C-PHY/D-PHY, eMMC 5.1, NVMe 1.2, USB 3.1
(Gen2) Superspeed+ and Power Delivery and xHCI 1.1, Unipro 1.6,
Soundwire, HBM, Toggle Flash, Automotive CAN, LIN, FlexRay.
NEW! -- DDR5, NVDIMM-P, CCIX, PCIe 4.0, AMBA 5 CHI, NVMe over Fabric,
HDMI, DP/eDP, I3C, SAS 24G "Save! Use all 53 VIPs with one license!"
User HiSilicon, Samsung, Broadcom, Xilinx, Marvell, SKHynix, SanDisk
(booth 229) Ask for Chris Browy. Freebie: cellphone mount
Oski AMBA FVIP Checker checks compliance to AMBA 5, CHI, AMBA 4,
ACE/AXI, AMBA 3, AHB-Lite, AHB. Funny story: The Oski VIP
out-performs Cadence VIP/ProofKits even on the JasperGold tool!
(booth 1139) Ask for Vigyan Singhal. Freebie: cellphone mount
SmartDV VIP claims 90 VIP and 41 sim acceleration IPs. (booth 1928)
MARGINs & ECOs
11.) Dorado Tweaker is a family of physically-aware ECO tools:
Dorado Tweaker-T1 vs. PrimeTime-ECO vs. Cadence Tempus-ECO
Dorado Tweaker-F1 vs. Cadence Conformal ECO
Static/dynamic power ECO's. 50 M inst. 16/14/10/7nm FinFET. Now
hierachical/timing/CPU/IR-drop ECO flows. Intel/GF/Samsung/TSMC
Broadcom, Qualcomm, LG, TSMC, Mediatek, Samsung, Altera users.
(booth 1620) Ask for JJ Hsiao. Freebie: fidget spinners
NEW! -- ICScape TimingExplorer-XTop physical MCMM timing ECO tool.
PBA timing fixes, route-based timing fix. 16/14/10/7nm 100M inst.
5X faster. ClockExplorer does CTS clock analysis and constraint
generation. Cuts clock insertion delay. Marvell, HiSilicon users.
(booth 1433) Ask for Jason Xing. Freebie: fidget spinners
Cadence Conformal ECO Designer generates "congestion-aware ECO"
for "last-minute difficult ECO areas". Broadcom, Qualcomm, ST.
(booth 107) Ask Kenneth Chang. Freebie: Denali party tix
Synopsys PrimeTime DMSA is all about distributed MCMM timing ECO's.
(booth 147) Ask for Robert Hoogenstryd. Freebie: pens
PRIMETIME & RIVALS
12.) Synopsys PrimeTime in 2013 was world's 87% marketshare STA tool. Now,
since we can't get independent stats, it's anyone's guess how much
Aart has lost to Anirudh's Tempus in the past 4 years. PT-SIG dinner.
(booth 147) Ask for Robert Hoogenstryd. Freebie: PT dinner tickets
Cadence Tempus this year is yarping up SmartScope, its "distributed
massively parallel STA with smart design abstraction to focus on user
chosen blocks or just top level analysis." 5x faster than Primetime.
Does ECOs, too. 250+ tapeouts. TI, NXP, LG, Maxlinear, ARM, TSMC,
GF, Sigma, Inphi, Softmachines, Analog Devices, Marvell, Qualcomm.
(booth 107) Ask for Ruben Molina. Freebie: Denali party tix
Arcadia TimeHawk STA is the "first commercial timer to bring AI, as
in artificial intelligence to timing signoff. Reduces pessimism by
countering inherent inaccuracy in STA models to achieve best SPICE
correlation." ECOs, 1+ M inst per minute, 2 billion capacity, SI.
(booth 915) Ask for Joey Lin. Freebie: pens
VIRTUOSO & RIVALS
13.) Virtuoso ADE is Tom Beckley's recent revamp of the CDNS ADE from the
old CDNlive'16 just 14 months ago. ADE Explorer is what was the old
ADE-L, but it has nominal/corners/sweeps/monte carlo/spec comparison
are now in one tool. ADE Assembler has multiple tests/statistical
(from GXL). Multi tests are not widely used, although popular in
some circles. The controversy is ADE Verifier -- Beckley is trying
to get circuit designers to do planning and design against design
goals in analog/custom design -- a very tough sell! (ESNUG 560 #1)
(booth 107) Ask for Steve Lewis. Freebie: Denali party tix
HOLY CRAP! -- Dan Clein just said that Virtuoso EAD actually *works*
now in ESNUG 571 #1! "Yes, it was launched a few years back, but
this is the time it finally works!" wrote Clein. EAD does real-time
in-design fast RC extraction, but with no LVS required. Layout
engineer gets immediate feedback on layouts to avoid "rip and repair"
syndrome. Aart is trying to copy these Virtuoso EAD ideas with his
Custom Compiler, but still he can't find any big Tier 1 buyers.
(booth 107) Ask for Steve Lewis. Freebie: Denali party tix
NEW! -- Virtuoso SDP is a seamless chip/package/PCB design flow. It
drives Spectre simulations and LVS-clean layout of ICs and multi-die
packages from a single hierarchical schematic. Does multiple ICs
designed with different PDKs. It's Sigrity going into Virtuoso.
(booth 107) Ask for John Park. Freebie: Denali party tix
Mentor Calibre RealTime does instantaneous sign-off DRC checking
inside Virtuoso, Laker3, and Custom Compiler. Same deck, same
results as batch Calibre. 2-5X productivity improvement when fixing
DRCs in 180-7nm nodes. Double/triple patterning, preferred metal
direction, density checks, pattern matching and voltage-aware DRC.
New cells/blocks-to-macros DRCs to automatically launching batch
Calibre jobs. Rivals Cadence iPVS. Qualcomm, Broadcom, Microsemi.
(booth 947) Ask for Srinivas Velivala. Freebie: K'Nex.
Synopsys Custom Compiler is Aart's 2nd attempt on Lip-Bu's Virtuoso
monopoly. The 1st try was Custom Designer (which flopped.) CC runs
the old Laker3 router plus the Ciranova Helix plus some "assistant
features" to generate many different layouts of one circuit.
(booth 149) Ask for Dave Reed. Freebie: pens
Silvaco Expert is a hierarchical IC layout editor. Schmatic driven.
10 Gig GDSII loads in "minutes". Uses Calibre Interactive for DRC
"on the fly". Rapid pan/zoom. Equal Resistance Router. OA and
interop PDKs (iPDK) makes design migration easier. And WTF???!!
Silicon Creations uses it for 10nm FinFET? Silvaco doing 10nm?!?
Also Silvaco Clever 3D RC field solver BEOL/MEOL parasitic extract.
(booth 1447) Ask Dave Dutton. Freebie: tote bags
Pulsic Animate does automatic layout of analog (transistor level)
designs, with no constraints, no scripting, no programming required.
Multi-threaded. Makes 100's of fully PnR-ed layouts in minutes from
an OpenAccess schematic (vs. 2-3 weeks single layout in Virtuoso).
Did a 40% reduction in cell block implementation time for Ricoh.
(booth 847) Ask for Mark Williams. Freebie: stuffed elephant
Mentor Tanner is OA-based S-Edit schematic capture, L-Edit custom
layout, and T-Spice SPICE. Founded 1988. "cost effective" prices.
New this year: old HiPer Verify DRC was replaced by Calibre DRC.
Also Pyxis stuff coming in, too. Aiming at MEMS and IoT markets.
(booth 1129) Ask for Jeff Miller. Freebie: pens
NanGate Library Creator II fine tunes std cells for slow transitions,
power, voltage. Also multi-bit cells (saves 25-30% dynamic power,
20-25% leakage), CPU/DSP datapath (8-14% less area). 20/16/14/10nm.
Also does coloring, self aligned MOL, template based cell creation.
(booth 241) Ask for Jens Michelsen. Freebie: pens
LibTech LibChar does std cell, IO, SRAM characterization & modeling.
Now does PLLs. (booth 841) Ask for Mehmet Cirit.
ClioSoft Visual Design Diff compares two versions of a schematic or
layout by graphically highlighting differences directly in Virtuoso
Supports IC 5.x (CDBA) and IC 6.x (OpenAccess). Does hierarchical.
Work with DesignSync & IC Manage. Can suppress cosmetic changes.
Batch mode to run diffs in the background and save state for later.
Infineon, Qualcomm, Bosch, Intel, Marvell, Toshiba, TSMC, Broadcom.
(booth 613) Ask for Karim Khalfan. Freebie: sun glasses
MunEDA WiCked SPT converts analog/mixed-signal/RF circuits across
different foundries/processes. Transistor resizing, optimization,
and verification for best performance, area, low-power/low-voltage,
robustness against process variation and mismatch. Qualified for
FinFET, Bulk, Bipolar, BiCMOS, and FDSOI. ST, GF, SMIC, HLMC users.
Their WiCked Circuit Suite does transitor resizing for PPA, too.
(booth 1012) Ask for Michael Pronath. Freebie: none
ICScape Skipper does super fast layout review, analysis, debug, and
layout IP protection. 1TB GDSII. Marvel, Hisilicon, SMIC, Sandisk.
(booth 1433) Ask for Jason Xing. Freebie: car tool kit
Keysight ADS and GoldenGate is for silicon RFIC design & simulation
New iPDK PyCell & TSMC iRCX support, more intuitive layout, does
electro-thermal on windows, harmonic balance & circuit envelope
converges faster. Qorvo, Skyworks, Broadcom/Avago, Qualcomm users.
(booth 1229) Ask for Nilesh Kamdar. Freebie: camping mugs
ClioSoft SOS RF does design data management for RF engineers using
Keysight Agilent ADS. Northrop, IDT, Quorvo, Rohde & Schwarz, Inphi
(booth 613) Ask for Karim Khalfan. Freebie: sun glasses
Intento ID-Xplore resizing/biasing/migration of analog/AMS circuits.
(booth 1920) Ask for Ramy Iskander. Freebie: stickers
DESIGN COMPILER & RIVALS
14.) Mentor Oasys-RTL does crazy fast RTL synthesis floorplanning, design
space exploration from "place first methodology". 3-hour runtimes
synth to floorplan a 2M inst chip 4G of machine memory. Synth-ed
and floorplanned 14nm 3M inst in 8 hours. 3.8M 28nm in 12 hours.
Designers can look at different views (logical, physical, timing).
TI, Broadcom, Juniper, Qualcomm use Oasys. Xilinx Vivado is Oasys.
(booth 947) Ask for Arvind Narayanan. Freebie: K'Nex.
Cadence Genus RTL is attack on Aart's 30 year Design Compiler
franchise. It's Anirudh's home-grown, massively parallel RTL and
physical synthesis tool that's "5X faster" than Design Compiler,
"1/2 iterations between unit and block/chip-level synthesis", and
has "timing/wire lengths within 5% of Innovus PnR", and has "20% less
datapath area!". Texas Instruments, Cisco, Maxlinear, and ImgTec.
User says 7nm with DC-G/Innovus took 55 hrs, with Genus/Innovus
it only took 25 hrs; also Genus predicted routability in 1.5 hrs.
(booth 107) Ask for Kam Kittrell. Freebie: Denali party tix
Synopsys demoing both Design Compiler Graphical and DC Ultra.
"Physical guidance to IC Compiler tightens correlation of timing,
area, and power to within 5% and speeds placement by 1.5X."
(booth 147) Ask for Gal Hasson. Freebie: pens
RTL & GATE POWER
15.) Calypto PowerPro does RTL power optimization. Users see 9% to 12%
general Verilog RTL power savings. 37% cut in sequential logic power
saving in ESNUG 535 #2. Chatting up their "What If" ability with
to quickly understand power effects of potential mode, operating
environment or design changes "saving hours of turn-around-time".
PowerPro is only tool that's tight with Calypto SLEC-Pro sequential
EC. Verifies low power RTL tweaks are equivalent to original RTL.
Users gush about Calypto PowerPro, but quiet about Ansys PowerArtist,
or Synopsys SpyGlass Low Power, or Cadence Joules in DAC'16 #9.
Has ~85% correlation against gate-level. 16/14/10nm FinFET.
Qualcomm, TI, Samsung, ARM, HiSilicon, Google, Freescale users.
(booth 947) Ask for Ellie Burns. Freebie: K'Nex
Apache PowerArtist users saw 3% to 10% reductions. Does automatic
and guided. Sequential and combinational clock-gating constructs,
memory light/deep sleep modes, and wasted power in datapath logic.
RTL power accuracy within 15% of sign-off. 10 M gates in an hour.
16/14/10/7nm. Handles 100M+ instances. Hooks with RedHawk for
power grid integrity. Also peak power & thermal hotspot analysis.
Has tight hooks into MENT Veloce emulation and Power App. Activity
streaming 10X faster vs. old slow FSDB for millisecs of activity.
Users are Broadcom, Nvidia, Samsung, ST, NXP, Toshiba, ARM, Ciena.
(booth 647) Ask for Preeti Gupta. Freebie: stuffed bulldog
Synopsys Atrenta Spyglass Power users got 9% to 16% power cut on
Verilog RTL. RTL, gate-level, or post-layout. FSDB, VCD, SAIF
and vectorless. Does ECO's, CPF, UPF, mem in sleep mode. ERC
checks on P/G netlist. Power modeling and coarse clock gating.
(booth 147) Ask for Piyush Sancheti. Freebie: pens
Cadence Joules is an RTL power calculator. Estimates power at RTL
to 15% of signoff power, time-based power up to 20X faster. This
year has "power scrubbers". "Oh, Joules works with Palladium, too!!"
(booth 107) Ask Rob Knoth. Freebie: Denali party tix
NEW! -- Baum PowerBaum does static & dynamic RTL power analysis that's
"100X to 200X faster" vs. PowerPro/PowerArtist/Spyglass. "We couldn't
find a fast/accurate tool to do this, so we built one of our own!"
(booth 639, Verific booth) Ask for Jinwook Jung.
CDNS JasperGold Low Power App formally verifies lower power designs
that have multiple voltage and power-management domains. Checks to
see any issues the after the insertion of power management circuitry.
(booth 107) Ask Pete Hardee. Freebie: Denali party tickets
LibTech ChipTimer does post-synthesis, pre-layout timing, area, power
optimization, and post-layout leakage power opto. Layout aware. 20%
to 2X less. "But we cut leakage power by 4X on a customer's 1.2M gate
16nm design using same library and no change in critical path timing."
(booth 841) Ask for Mehmet Cirit. Freebie: none
RTL ENVIRONMENTS/SIMULATORS/TOOLS
16.) Synopsys Verdi3 is the wildly popular design debug waveform viewer
with a Qt-based GUI. Aart got it with SpringSoft. Man, it does
everything! UVM, OVM, System Verilog, VHDL, SVTB, VMM, SVA, CDC,
FSBD, UPF/CPF, nWave, nSchema and TFV, PDML, CTS, SDC, STA, HW/SW.
(booth 147) Ask for Thomas Li. Freebie: pens
Verifyter PinDown auto debugs regression failures by IDing the
commits that cause the test failures and automatically assigns bug
reports to the engineers who made these commits. PinDown now debugs
down to the exact line of code. Samsung, Broadcom, Synopsys users
(booth 2013) Ask for Daniel Hansson. Freebie: chocolate kisses
Defacto Star Design tools is an 8-part unified RTL design flow where
coherency between Verilog/VHDL RTL, SDC, IP-XACT, UPF, and SystemC
is guaranteed. Builder does RTL design editing and exploration.
Checker does simulation-free connectivity checks. Low Power does
UPF design exploration. Other parts do padring, DFT, IP, etc. See
review in ESNUG 530 #2. Users Qualcomm, Broadcom, Intel, Maxim-IC.
(booth 1220) Ask for Chouki Aktouf. Freebie: candy
MENT Questa Platform bundles all Mentor Verilog/VHDL RTL simulation,
emulation, low power, VIP, traffic generators, interconnect test,
intelligent testbench, coverage, UVM, formal in one big smudgy bundle.
Now has ISO 26262 certification, and enhanced real number modeling.
(booth 947) Ask for Mark Olen. Freebie: K'Nex
SNPS Verification Continuum bundles all the Synopsys simulation stuff
yada, yada, yada... exactly like the MENT and CDNS marketing does...
(booth 147) Ask for Manoj Gandhi. Freebie: pens
Aldec Riviera-PRO simulates System Verilog, VHDL, Verilog and SystemC.
The Plot Viewer does simple/polar/vector graph and image/color map.
Python support using Cocotb GPI. This enables terse, readable,
maintainable code while providing easy Python abstraction to RTL.
(booth 421) Ask for Christina Toole. Freebie: texas longhorn dolls
Amiq Eclipse DVT IDE is an add-on to VCS/Questa/Incisive that lets
an engineer NOT have to continuously switch between his editor and the
"e"/SystemVerilog/VHDL simulator. IDE is sorta like Visual C stuff.
(booth 1731) Ask for Cristian Amitroaie. Freebie: horseshoes?
Sigasi Studio is much like Amiq DVT. Now has System Verilog support.
(booth 1922) Ask for Hendrik Goossens. Freebie: pens
Agnisys DVinsight is a friendly editor for UVM developement sort of
like Amiq. Helps your write code. And their IDesignSpec converts
specifications for registers/sequences into UVM/RTL. NASA, Intrinsix,
HGST, Icron, Conexant, Wipro, Conexant, John Deere, CERN uses Agnisys.
(booth 223) Ask for Anupam Bakshi. Freebie: beer bottle opener
HARD & SOFT IP
17.) ARM showing new Cortex-A75 CPU, Mail-G72 GPU plus its 32/64-bit
RISC CPUs, memory IPs, Artisan std cell libs, plus ARM Socrates
for IP configuration & SoC assembly, plus ARM Coresight/CoreLink
(booth 729) Ask for Brenda Wescott. Freebie: pens
Synopsys is showing its Virage DW ARC 600 & 700 cores, plus
mem IP, plus std cell libs; that all directly compete against ARM.
New is DW ARC HS4x and HS4xD processors. 6000 DMIPS per core.
ARC now has 226 customers. DW ARC comes in low power and audio.
(booth 147) Ask for Mike Thompson. Freebie: pens
Cadence IP Portfolio has interface IP for USB, PCIe, MIPI, Ethernet;
analog mixed-signal IP for SerDes, ADC, DAC, AFE, power management;
peripheral IP for I2C, I2S, PWM; Denali memory IP for DDR, LPDDR,
WideI/O, NAND Flash; Tensilica for baseband, audio, imaging/video.
This year has new fully verified/certified PCIe Gen4 and CCIX.
(booth 107) Ask for Sachin Dhingra. Freebie: Denali party tix
Silvaco Xena scans a chip-level database to list all detected IP and
versions of that IP. Works for embedded SW, too. It scores the
extent to which IP exists in the chip, from its entirety to fragments.
(booth 1447) Ask for Warren Savage. Freebie: phone ear buds
NEW! -- Cadence Tensilica Vision C5 claims "first DSP IP for neural
network processing". 1TMAC/sec in 1mm2 in 16nm. 6X faster in AlexNet
CNN benchmark, 9X faster Inception V3 CNN benchmark than its rivals.
(booth 107) Ask for Gerard Andrews. Freebie: Denali party tix
NanGate IoT Std Cell Libs are "IoT optimized" full custom libraries.
9000 cells, 5 VTs, 3 gate lengths. 28/40/65/90nm silicon proven. Cut
area by 8-14%. "Our 8T 28nm GF lib got 55% higher raw gate density."
(booth 241) Ask for Jens Michelsen. Freebie: pens
Analog Bits is what its name implies: low power, small footprint
28 nm IP for precision clocking, PLL, DLL, SERDES, SRAM, TCAM, IO.
(booth 1241) Ask for Mahesh Tirupattur. Freebie: none
CAST has a mess of 8051 cores, GPU and accelerator IP cores, CAN FD,
H.264 encoders, JPEG IP. New Geon "secure" uP, J2716, MIL-STD 1553.
(booth 1124) Ask Nikos Zervas. Freebie: stylus pen
EnSilica Ltd. sells configurable 16/32-bit eSi-RISC, eSi-Crypto,
eSi-Comms, eSi-Connect. (booth 1430) Ask for Ian Lankshear.
Omni Design sells ADCs, DACs, bandgaps, oscillators, LDOs, temp
sensors. 28nm to 180nm. For IoT. (booth 1921) Ask Denis Daly
Silicon Creations LLC sells Fractional-N PLL and SerDes IP that's
"proven on 20 process nodes". Now multiple proven 7nm PLLs this year.
Avago, TSMC, SMIC, UMC, GlobalFoundries, Samsung, ARM, DongBu, Toshiba
(booth 1441) Ask for Andrew Cole. Freebie: USB car chargers
.
SiLab Tech sells USB 3.1 PHY, Serdes, MIPI, high speed ADC & DAC,
low jitter PLLs. (booth 1529) Ask for Yossi Yehiel.
True Circuits sells IP for low-jitter PLLs and DLLs for TSMC, UMC,
GloFlo, CP 180nm to 16FF+. (booth 1327) As for John Maneatis.
Uniquify SuperCombo is interface PHY and LPDDR3/4-DDR3/4 controllers.
3200Mbps per pin 28nm LP. 20-30% smaller area than competition.
Samsung, LG, Sigma Design, Telechips, Panasonic, Socionext users.
(booth 521) Ask for Raman Prodduturi. Freebie: USB ballpoint pen
BIG DATA & ANALYTICS
18.) IC Manage Envision is a tapeout predictor based on Big Data. It was
the #1 Cheesy Tool of DAC'15. After data mining 2 years company-wide
man-hours and 28nm EDA tool run logs, Xilinx used Envision to predict
their Zynq 20nm migration tapeout to within +/- 1 week. ESNUG 550 #1.
New this year is Verification Dashboard of job submissions to LSF,
with real-time job monitoring, results parsing, historical analysis,
aggregated analytics. Dynamic Graphs, custom field expansion.
(booth 1539) Ask for Steve Klass. Freebie: candy
Consensia PinPoint is web based analytics on every aspect of
ASIC/FPGA design from synthesis, CDC, STA, CTS, power to layout, so
design teams get to design closure faster. Qualcomm, Avago users.
Is this the old Tuscany PinPoint that Dassault bought 5 years ago?
(booth 1041) Ask for Dave Noble. Freebie: stress ball
TEST/SCAN/BIST/JTAG/FAULTS
19.) Here's why Wally's test brainiacs beat out Aart in ATPG/scan test.
Mentor TestKompress does hierarchical ATPG. Patterns are generated
independently for each core. Can be retargeted at chip top-level.
10x faster generate time and 1/10th CPU time of Synopsys TetraMAX.
Pattern count is 1/2, so less test time. Also this core-level ATPG
means no wait for whole design to be done before ATPG generation.
TestKompress now does end-to-end hierarchical, which takes DFT out
of the critical path, reduces ATPG and diagnosis runtime by 10X,
and pattern count by another 2X. Users are Broadcom, NXP, Renesas,
On Semi, Intel, NXP, Mediatek, Spreadtrum, and Annapurna Labs.
Mentor Tessent ScanPro places test points in netlist for compression.
Adding 1%-2% area for a 3X to 4X reduction in ATPG test patterns.
If 100X compression with TestKompress, ScanPro gets 300X to 400X.
(booth 947) Ask for Geir Eide. Freebie: K'Nex
Cadence Modus Test does scan insertion, compression, ATPG,
logic and memory BIST. Physically aware 2D elastic compression
that cuts test logic wirelength by 2.6X. Compression ratios of
400X. Takes 1/3rd tester time. Works with CDNS Genus RTL synth.
PMBIST. Soft programmable test for FinFET SRAMs and automotive.
Texas Instruments, GlobalFoundries, Microsemi, Sequans users.
(booth 107) Ask for Rob Knoth. Freebie: Denali party tix
NEW! -- Mentor Tessent MissionMode does hardware functional safety
stuff by system-level low latency access to on-chip test resources
for on-line test and diagnosis. Works with Tessent LogicBIST
and Tessent MemoryBIST or other 3rd-party IJTAG compliant test IP.
Mentor Tessent DefectSim does transistor-level fault simulation for
analog, mixed-signal, and non-scan digital circuits when test quality
must be measured, or improved, or maintained while test cost is cut.
It automatically calculates all necessary ISO 26262 hardware safety
metrics like SPFM, LFM, DC and PMHF. Users are On Semi, AMS AG.
(booth 947) Ask for Steve Pateras. Freebie: K'Nex
Mentor Tessent Diagnosis and YieldInsight uses failing test data to
find logic & physical layout yield problems "in days, not months."
Spots systematic yield issues at transistor level. Samsung, Cypress.
Mentor SiliconInsight ATPG used to be memory/logic BIST
diagnosis through a JTAG port. Now uses $100 USB port to access
64 pins. See which scan cells failed or co-ordinates of defects.
Debug ATPG, MBIST, LBIST and IJTAG issues without valuable ATE time.
(booth 947) Ask for Matt Knowles. Freebie: K'Nex
Synopsys SpyGlass DFT does "RTL analysis for stuck-at/at-speed
testablity, low power design, JTAG/IEEE1500" and "RTL fault coverage
estimation for stuck-at, transition and random-resistive faults."
(booth 147) Ask Kiran Vittal. Freebie: pens
Synopsys WinterLogic Z01X Safety does fault injection and simulation
(DC, AC, transient faults) for ISO 26262 and IEC 61508 compliance.
Works with SNPS Certitude and rivals CDNS Verifault-XL. User Denso.
(booth 147) Ask for Jason Campbell. Freebie: pens
FPGA STUFF
20.) Mentor Certus does silicon debug for FPGAs, FPGA Prototypes and ASICs.
It rivals Xilinx ChipScope, Altera SignalTap, Synopsys Identify.
"Traced 500 AXI bus signals of a Linux boot sequence (180 seconds)"
(booth 947) Ask for Michael Sachtjen. Freebie: K'Nex
NEW! -- Plunify Kabuto is machine learning to give RTL fixes for FPGA
designs based on timing path/RTL analysis -- e.g. you need to pipeline
a design, it suggests code needed to ensure dependencies are checked
properly. Not linting tool; it fixes bad RTL timing paths.
(booth 1631) Ask for Kirvy Teo. Freebie: fidget spinners
Menta eFPGA Origami is a unique tool that lets ASIC/SoC designers
create their own TSMC 28HPC+ or GF 14LPP embedded custom FPGA IP blocks.
(booth 1329) Ask for Yoan Dupret. Freebie: ment candy
OneSpin 360 EC-FPGA does equivalency checking RTL vs. post-synthesis
netlists for FPGA's. (booth 1547) Ask for Raik Brinkmann.
ROLL-YOUR-OWN EDA SOFTWARE STUFF
21.) Verific sells System Verilog and VHDL parsers with C++ interfaces to
EDA developers. Perl interface. Parsers for UPF 2.1, PSL, EDIF.
Python APIs. Synopsys, Atrenta, Xilinx, Altera, AMD, Infineon users.
Has a new UPF elaborator that does really clever power-cell stuff.
(booth 639) Ask for Michiel Ligthart. Freebie: stuffed giraffe
Mirabilis Collaborator generates docs and javascript for executing
models within a web browser. Used as specification or a customer
demonstration tool. Does parameter/algorithmic/topology changes.
(booth 2221) Ask for Deepak Shankar. Freebie: toothbrushes
OneSpin 360 LaunchPad lets companies with no formal tools develop
and deliver formal-based apps inside their own in-house EDA SW.
(booth 1547) Ask for Raik Brinkmann. Freebie: fidget cubes?
WORKSPACE, DESIGN DATA MANAGMENT, & IP TOOLS
22.) IC Manage PeerCache gives 10x speed up for ALL EDA tool I/O (layout,
regressions, PnR...) Removes NFS bottlenecks. Reduces disk space 90%.
Fast copies for ALL files, not just DM-managed ones. Machine Learning
analytics for Security. 100% software fits everywhere. (ESNUG 571 #5)
(booth 1539) Ask for Shiv Sikand. Freebie: candy
NEW! -- ClioSoft designHUB is where project engineers can create and
upload IPs, browse, search and compare available IPs, easily track
the IP lineage, issues, defects and their resolutions. "It's a
one-stop-shop for all designs within a company immaterial of where
the design data is physically located - SOS, Perforce, Git,
SubVersion or any network storage." Skyworks uses designHUB.
(booth 613) Ask Ranjit Adhikary. Freebie: steel cup
IC Manage GDP design & IP data management system lets digital/custom
designers find, modify, release & track design data through tapeout.
Their nGDP is flexible, multi-tier web stuff, mixed docs/graph DB.
Samsung, Intel, AMD, Xilinx, Nvidia, Qualcomm, Nokia Networks, UBlox.
(booth 1329) Ask for Alex Tumanov. Freebie: Candy
ClioSoft SOS7 does HW configuration management and rev control for
Virtuoso, Laker, Pyxis, Custom Compiler, Keysight ADS. Built-in IP
management and reuse. Does soft integrations with in-house flows.
Now better security, improved IP traceability, Jenkins integrations.
Huawei, Google, Analog Devices, Infineon, Toshiba, Marvell, TSMC
(booth 613) Ask for Karim Khalfan. Freebie: steel cup
Mentor Questa VRM is verification run management system that combines
coverage metrics from formal, CDC, simulation, and emulation engines.
Accellera UCIS standard, and Jenkins regressions. Nokia & Micron.
(booth 947) Ask for Mark Olen. Freebie: K'Nex
Consensia DelphIP does enterprise IP mgmt for ITAR 3rd party IP. Now
does defect tracking. Competes against Oracle Agile or Siemens PLM.
(booth 1041) Ask for Dave Noble. Freebie: pressure ball
Cadence vManager is just like Questa VRM, but this year vManager has
a new API bug systems, source systems, or agile development systems.
(booth 107) Ask for John Brennan. Freebie: Denali party tickets
Methodics Percipient is a "new graph database providing customers 5X
performance improvement in IP data management and analytics." It
also does "issue and defect management and requirements management".
Samsung, Micron, Silicon Labs, Cirrus Logic all use Percipient.
(booth 1513) Ask for Simon Butler. Freebie: live jazz music
Runtime WorkloadXelerator is hierarchical enterprise job
distributed computing environments. It removes the scheduler as a
bottleneck to compute resources, allowing compute farms to be scaled
up without re-architecting the data center. +10 M jobs per day.
Useful for verification regression testing or massive SPICE runs.
LicenseAllocator cuts license cost by maximizing multi-site sharing.
NEW! -- Runtime Hero high perf scheduler for hardware emulation.
Has emulation-specific metrics yet "emulation vendor independent."
(booth 321) Ask for Stuart Taylor. Freebie: shot glasses
Fractal Crossfire does format consistency checks on hard IP? Huh?
(booth 939) Ask for Felipe Schneider, Freebie: none
NEW! -- ICScape Qualib also does format consistency checks on hard IP?
But whatever it is, Marvell, SMIC, and HiSilicon are using Qualib.
(booth 1433) Ask for Jason Xing. Freebie: fidget spinners
Anyway, I hope this helps! I'm easy to spot: just look for the tall, fat
confused white guy who looks like he shouldn't be there. That's me! :)
- John Cooley
DeepChip.com Holliston, MA
P.S. And if you found this floor guide useful, please email me. It's a LOT
work at a VERY crazy time of year for me to put this together.
-----
John Cooley runs DeepChip.com, is a contract ASIC designer, and loves
hearing from engineers at or (508) 429-4357.
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