Editor's Note: First off, let me say that if Nassda is guilty of hands-on
theft of Synopsys source code, Nassda deserves to be punished. But one
aspect of this Synopsys vs. Nassada lawsuit story bothers me:
The ruling doesn't necessarily mean that code was literally copied.
"'Derived' means that you take knowledge of our code and use it to
write other source code a lot more quickly, leveraging our work
to produce a new product faster," Jackson said.
I know Synopsys and Cadence (and probably Mentor and Magma) like to force
their workers to sign "Zombie-Slave" contracts. The "Zombie" clause says
we-own-everything-you-ever-think-of. The "Slave" clause says you-can't-
work-for-any-rival-for-X-years. My weak understanding of California law
is that these contracts aren't that enforcable (something about California
being a Right To Work state or something) so they pretty much boil down
to if-you-leave-us-our-lawyers-will-screw-with-you-and-though-we-won't-
win-we'll-curse-you-with-massive-legal-bills-to-pay-defending-youself.
My fear is that this lawsuit is seeking a precedent to make Zombie-Slave
employee contracts enforceable. A good 95% of EDA innovation comes from
ex-Synopsys, ex-Cadence, and ex-Mentor employees coming up with an idea
for a better EDA product and giving it a try in a start-up. Look at
Synplicity, Silicon Perspectives, Apache, Magma, 0-in, Verisity, CoWare,
Chronologic, ModelTech, Get2chips, IKOS, Sierra, Plato, Simplex, ...
they're all ex-Synopsys, ex-Cadence, and/or ex-Mentor employees. Won't
enforced Zombie-Slave contracts pretty much kill off innovation in the
EDA industry? Am I wrong to have this fear?
- John Cooley
the ESNUG guy
( ESNUG 430 Subjects ) ------------------------------------------- [06/16/04]
Item 1: Net Naming Tricky When Using Calibre with TestKompress Diagnostics
Item 2: A False Equivalence Warning for Formality 2003.06 and 2004.03
Item 3: compile_new_optimization Turns On Gain-based Synthesis in DC?
Item 4: ( ESNUG 428 #1 ) Verisity Axis Rebuttal To The Palladium Benchmark
Item 5: ( ESNUG 427 #1 ) Jim Questions Xilinx Slices Used In Benchmark
Item 6: ( DVcon 04 #9 ) How To Get Black Box Abilities In Verplex LEC
Item 7: Our DC, Magma, Hercules, Star-RC, PrimeTime, Artisan, IBM Tape-out
Item 8: User Wonders "Why Does Synopsys Promote VCS & Vera Over Magellan?"
Item 9: ( ESNUG 429 #5 ) AstroRail Uses Power Sources At Multiple Levels
Item 10: ( DVcon 04 #10 ) One User's Hands-on Eval of Jasper JasperGold
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
============================================================================
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/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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