( ESNUG 430 Item 5 ) --------------------------------------------- [06/16/04]
Subject: ( ESNUG 427 #1 ) Jim Questions Xilinx Slices Used In Benchmark
> Xilinx - ISE 5.2 : SLICEs used 75%
>
> The tool has several problems with added/changed complexity of the design
> (may crash with fatel error). Largely simple to use and setup. Newer
> version 6.1 is to support Linux and Solaris in native mode. On the PC
> some of the crash errors has been fixed.
>
> Synplicity - Synplify Pro 7.3.1 : SLICEs used 91%
>
> The GUI is simple to use and has good integration with the ISE P&R part.
> For several other designs it is known to produce better results than ISE.
From: Jim Lewis <jim=user domain=synthworks got calm>
Hi, John,
This guy used Xilinx slices as a measure of the quality of the synthesis
results. Based on the Xilinx seminar I attended recently, I don't believe
this is a proper metric.
In the seminar, the Xilinx AE discussed the issue of slice utilization and
improvements in their reports specifically targeted at getting a better
understanding of device utilization.
They explained that currently, if the device is not particularly full,
synthesis tools can liberally use slices to give maximum flexability when
placing and routing the design. The objective being to reduce the impact
of routing delays.
For the results shown to be valid, they need to be numbers from the current
release of the Xilinx tools. Xilinx no longer presents strictly a slice
count, so I would conclude that they are not.
A more accurate benchmark would take the results from each synthesis tool,
place and route them in Xilinx, and then provide the mapper report from
Xilinx, or at least the following information. I suspect this would also
require locking the pinout so all designs are considered equally.
Logic Utilization:
Number of Slice Flip Flops: 75 out of 1,536 4%
Number of 4-input LUTs: 109 out of 1,536 7%
Logic Distribution:
Number of occupied Slices: 75 out of 768 9%
Number of Slices containing only related logic: 75 out of 75 100%
Number of Slices containing unrelated logic: 0 out of 75 0%
Total Number 4-input LUTs: 116 out of 1,536 7%
Number used as logic: 109
Number used as a route-thru: 7
Related logic is defined as being logic that shares connectivity, e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing it into
a slice once 99% of the slices are occupied through related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
In addition to the mapper reports, it would also be meaningful to have the
timing reports from the Xilinx tools of the placed and routed designs. It
would be interesting to see how close they are to the timing specification
(how much margin or lack of it). If the design does not meet timing small
results are meaningless.
Having done Actel and Altera designs with older Synopsys tools, it would be
interesting to see if Synopsys has miraculously gained a better
understanding of FPGAs. I would have to see it myself to believe it.
- Jim Lewis
SynthWorks VHDL Training Tigard, OR
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