"If you want to deal with interesting problems, engineering is
it. If you want to be respected, and, on average, you want to
make a fair amount of money, go into something else."
- Gabe Moretti
EDN's EDA Editor
( ESNUG 424 Subjects ) ------------------------------------------ [03/09/04]
Item 1: User Finds Unreleased Ver. Of DC (Nighthawk2) Has Faster Runtimes
Item 2: ( ESNUG 423 #13 ) Richard & Peggy's Take On The DVcon'04 CEO Panel
Item 3: Ray Clarifies The Cadence Product Stance On System Verilog
Item 4: ( DAC 03 #31 ) Another User's Impressions Of Apache RedHawk-SDL
Item 5: Odd Zero Width Glitch Test Results for Verilog-XL vs VCS 6.0*/7.0*
Item 6: ( ESNUG 421 #10 ) Magma BlastRail, EM, STA, and IR-drop Delays
Item 7: Gzim Discovers & Then Rediscovers A Nasty Tcl "{" Commenting Bug
Item 8: What Are The Real Synopsys, Cadence, Magma 90 nm Usage Numbers?
Item 9: ( ESNUG 420 #3 ) Nassda HSIM With Cadence NC-Sim & NC-Verilog
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@TheWorld.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
|
|
