( ESNUG 424 Item 5 ) -------------------------------------------- [03/09/04]
From: Ken Wong <wong=user domain=sd.conexant spot calm>
Subject: Odd Zero Width Glitch Test Results for Verilog-XL vs VCS 6.0*/7.0*
Hi, John,
I want to test if a zero width glitch in Verilog can cause VCS to hang
or lock in infinite loop. Here's my simple Verilog source file used
for the test:
// zero width glitch to test if VCS will hang
module test;
reg [3:0] a;
reg [3:0] b;
initial
begin
a = 0;
b = 0;
#10;
a=5;
b=10;
#10;
$display("Reached End.");
$finish;
end
always @(a)
begin
b=10;
$display("Changing always block B");
b=0;
end
always @(b)
begin
a=5;
a=0;
end
endmodule
To my surprise I could not get VCS to hang, with or without +delay_trigger
option. I tested versions 6.0* and 7.0*.
For comparison, my Verilog-XL simulation does not hang with +delay_trigger,
but hangs without it. I suppose such behavior is IEEE 1364 compliant, but
I could be wrong.
Unsure why the difference between VCS and Verilog-XL, I would like to ask
the ESNUG community for any insight.
- Ken Wong
Conexant Systems, Inc. San Diego, CA
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