> Yet, this month, he's doubled his personal net worth investing in
> IPO's!!! Now his catch phrase is "Why bust your hump slaving for a
> start-up when you can make the same money investing in them!" Now he's
> even seriously thinking of putting a second mortgage on his house for
> extra money to put in the stock market. I hope we successfully talked
> him out of it. Hmmm... Man... Doubling his personal net worth in
> less than a month... Damn. I can see his temptation. Damn...
>
> - John Cooley
> the ESNUG guy
From: Dan Gillmor <dgillmor@sjmercury.com>
It is tempting, John, it is tempting...
- Dan Gillmor, Tech Columnist
San Jose Mercury News San Jose, CA
---- ---- ---- ---- ---- ---- ----
From: James Ma <jhma@bugrug.eng.sun.com>
John,
You hardly need to risk investing in IPOs to make money. SUN has more
than doubled this year. Qualcomm has gone up 600% this year. Dell went
254% last year. Not quite as fast as a month but a year is not that long
and these stocks are safe. They actually have serious revenue and make
lots of money.
- James Ma
Sun Microsystems
( ESNUG 337 Subjects ) ------------------------------------------ [11/99]
Item 1: ( ESNUG 331 #1 336 #1 ) Replies On The P&R Hierarchical/Flat War
Item 2: DC 99.05 Scripts Converted To Tcl Work In 99.05 But Not In 99.10
Item 3: ( ESNUG 334 #2 ) full_case/parallel_case, Evil Twins of Synthesis
Item 4: Better Multipliers Without Having To Buy A Pricey DesignWare Lib
Item 5: ( ESNUG 336 #3 ) Sarcastic Replies On Xilinx's "New" Web Presence
Item 6: ( ESNUG 336 #10 ) Concerning The Way To Insert BIST Question
Item 7: Help! Gzim's Being Burned By The "is_hierarchical" Attribute!
Item 8: Cliff Trashes Navabi's New "Verilog Digital System Design" Book
Item 9: What Are The Gotchas Concerning Using Behavior Compiler w/ FPGAs?
Item 10: We're Stuck Doing Our Own SpeedChart Y2K Compliance -- Any Ideas?
Item 11: An On-Line Tutorial On How To Synthesize SUN's picoJava Core
Item 12: Free DES Encryption/Decryption Plus Synplicity vs. FPGA_Express
Item 13: ( ESNUG 336 #5 ) Veritools' Undertow Can Display Raw SPICE Output
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 337 Item 1 ) -------------------------------------------- [11/99]
Subject: ( ESNUG 331 #1 336 #1 ) Replies On The P&R Hierarchical/Flat War
> I've been doing P&R for years. Let me let you in on two foundry secrets.
> The first secret is that the average design today is 200 to 300 kgates.
> We tell our customers that our average design is 750 kgate to 1 million
> gates, because that's what our customers want to hear and what our
> Marketing department tells us to say. Reality is 200 to 300 kgates.
>
> - [ There's A Sucker Born Every Minute ]
From: "Gary Smith" <gary.smith@gartner.com>
Hi, John,
The hard data on this partially agrees w/ [ Sucker Born ]. Our 1999 survey
of hardware engineers in the U.S. market for ASIC design breaks out as:
24 % ######################## less than 100 k gates
22 % ###################### 100 to 249 k gates
4 % #### 250 to 499 k gates
16 % ################ 500 to 999 k gates
22 % ###################### 1,000 to 2,499 k gates
4 % #### 2,500 to 4,999 k gates
4 % #### 5,000 to 10,000 k gates
2 % ## 10,000 + k gates
Worldwide, there are about 10,000 ASIC design starts.
- Gary Smith, Senior EDA Analyst
Dataquest San Jose, CA
---- ---- ---- ---- ---- ---- ----
> Aart should give a big bonus to the slick Synopsys salesman who sold
> FlexRoute to SGI. They didn't need it.
>
> - [ There's A Sucker Born Every Minute ]
From: Pravin Madhani <pmadhani@synopsys.com>
Hi John:
I wanted to set the record straight that it was not some "slick Synopsys
salesman who sold FlexRoute" to SGI. As you know, FlexRoute technology
was developed at Everest Design Automation. SGI was a customer of Everest
*before* Everest was acquired by Synopsys and the product released at
what we now call FlexRoute. SGI was quite unhappy with their old solution
and looking for alternatives. They were very impressed with the Everest
technology and the team. Even though we were a small startup with a short
history, SGI decided to purchase and use our router. From the perspective
of Everest, as any start-up with hot technology to prove, we were also
looking to engage with design teams doing truly challenging designs. We
found that in Sam's team at SGI. I am thrilled that FlexRoute was able to
make such a difference as help "improve their transistor density by 25%".
I'll now return you to your previously scheduled technical discussion...
- Pravin Madhani, ex-CEO of Everest Design Automation, Inc.
Synopsys
---- ---- ---- ---- ---- ---- ----
> The second secret is Avanti easily does place & route on *FLAT* designs of
> 200 K instances in 24 hours. YOU DON'T HAVE TO DO ALL THAT HIERARCHICAL
> CRAP SYNOPSYS IS PUSHING!!! Sam could have intelligently partitioned his
> 750 K instance design into four parts by hand and Avanti could take it
> from there. No brainer. Kick off Avanti on 4 workstations with lots of
> CPU cycles and memory. Come back the next morning. Glue the 4 parts
> together. Your final detailed placement and routing is done. FlexRoute
> and its complicated hierarchical games are a waste of engineering time and
> money.
>
> - [ There's A Sucker Born Every Minute ]
From: "Sam Appleton" <sama@groovy.mti.sgi.com>
Hi John,
I certainly appreciate the comments, both good and bad, that ESNUG 331
generated. Most people seem to fall into two camps -- those who use
hierachial design and those who despise physical hierachy.
I'd like to respond to some of the comments made by [ There's A Sucker Born
Every Minute ]. I agree that for small 250k instance designs hierachy is
not necessary if there are no hard timing or signal integrity issues to
address. The tool (Cadence or Avanti) will cope with sizes that big, most
clock/extraction/delay calculation tools work with designs that size, and
it's generally a slam dunk. No real data management issues to contend with
either.
But as to doing flat layout on a 750k instance design - really? I am
mystified by a couple of statements
"Sam could have intelligently partitioned his 750 K instance design
into four parts by hand and Avanti could take it from there."
How do you "intelligently partition" a design into 4 pieces in the tool?
Does it magically fit together? Does Avanti support this? Cadence doesn't.
Do you arbitrary break the design along a global placement, or do you BREAK
THE DESIGN BY LOGICAL HIERACHY? If you break the design by logical
hierachy, then it certainly sounds like you're doing hierachial physical
design, and you'll have to do pin assignment, interconnect routing etc
between the pieces. Avanti must have some great magic in it. If you're
doing things by abutment, a host of other issues come up, like signals that
go between multiple blocks, signals that want to cross one partition to
get to another block, etc etc etc.
"Come back the next morning. Glue the 4 parts together. Your final
detailed placement and routing is done."
How is this magic performed? Glue the 4 parts together? How do you insert
a clock network over designs this size and then "glue" them together? How
do you deal with post-layout netlist issues (i.e. the tool modifies the
netlist for clock, scan and possibly IPO buffer insertion). How do you
deal with interconnection issues between the pieces?
I've asked people who use Avanti tools how this could be done -- they
are equally baffled.
With our experience, some things become impossible in flat designs:
o clock insertion -- do you really believe what CtGen or the equivalent
Avanti tools tell you about insertion delay and skew? They're
pre-routing results that don't mirror the actual layout results all
that well, and their parasitic estimates (which have HUGE impact on
skew) are always way off, since they're 2D estimates only. Try
extracting your clock net and SPICE'ing it -- you'll be surprised.
o signal integrity -- yes, we had buses that travelled 11mm. Cell-based
routers SUCK at routing these signals, plus you need specialized
width/spacing rules to deal with crosstalk-induced delay issues on
these lines. The meandering routes produced by cell routers on such
nets are unacceptable! They produce huge numbers of unnecessary layer
changes, and wire lengths that are far longer than the unrouted net
length. For signal integrity on the critical top trunks of the clock
net, these wires need to be routed on very wide wires over distances of
3-7mm, with special spacing characteristics to avoid signal integrity
and electromigration problems. Do cell-based routers do this at all
well? Absolutely not.
o extraction -- we could not extract a 750k instance design flat. Maybe
we weren't doing something right, or maybe we should have used
Report->SPF out of Silicon Ensemble's 2D extractor and used that? With
hierachy, we could start with a bunch of GDS2's and get to full-chip
SPF in a couple of days with a 2-1/2D extractor, incrementally change
parts of the design and re-extract in hours, and do hierachial delay
calculation. Flat layout would not allow that degree of performance at
the extraction end.
Yes, we were easily duped by the non-existent slick Everest salespeople that
called on us. They walked in, said "we have a top-level router that's
really nice, and it's for hierachial design". Instantly, we dropped all
our marbles and paid big bucks for a waste-of-money tool. We're _that_
gullible. No wonder Synopsys bought them.
> Tell Sam good review. Lots of details. Please ask him whose placement
> tools he used. He nixed Avanti and Cadence for routing, but said nothing
> about what he used for placement. Did he use Qplace, Avanti, or Chip
> Architect? Aristo? Anon. pls.
>
> - [ Party Like It's 1999 ]
Thanks for the comments from [ Party Like It's 1999 ]. For our block-level
tools, we used:
o Cadence Qplace for timing-driven placement
o Cadence Wroute for routing
Qplace and Wroute are fine for block-level stuff, mostly. Wroute doesn't
deal with wide wires or signal integrity on wires very well at all, at least
not in the incantation we used (5.1.xxx). I know Cadence/Avanti/Synopsys
all have new cell placement/IPO/placement-based-synthesis technology that
we'd really like to evaluate.
FlexRoute is a great tool if you're doing large designs and you're concerned
about things like route quality, chip density, timing convergence, and
clock/signal integrity. If your chip is small and these issues don't
concern you greatly, and it fits easily into the space of a P&R tools'
capacity, then flat is probably a better way to go.
- Sam Appleton
SGI Mountain View, CA
( ESNUG 337 Item 2 ) -------------------------------------------- [11/99]
From: George Hwa <hwa@rtda.com>
Subject: DC 99.05 Scripts Converted To Tcl Work In 99.05 But Not In 99.10
John,
I found numerous useful tips on the DC-Tcl mode from your previous DeepChip
archives. However, my adventure takes into the deep deep stuff...
I'm converting a set of DC scripts to Tcl and from 99.05 to 99.10. The
converted Tcl scripts work fine in 99.05 but are failing in 99.10 without
much useful feedback from the tool. Any insightful ideas?
- George C. Hwa
Runtime Design Automation Sunnyvale, CA
( ESNUG 337 Item 3 ) -------------------------------------------- [11/99]
Subject: ( ESNUG 334 #2 ) full_case/parallel_case, Evil Twins of Synthesis
> But Cliff also says (in 3.3) that using a default: out = 'bx; also isn't
> good because then your simulation & synthesis don't match.
>
> Here I disagree. I think you're trying to optimize the wrong part of
> the design: simulation vs. gates match. In doing so, you're giving up
> some of the power of RTL simulation. In RTL I'm able to write code
> in such a way that my logic will blow up to X's when a make a false
> assumption. (i.e. I *believe* the case to be fully specified, if it's
> not, I want X's introduced into my sims, not some latch function or
> other valid input - X's are easy to detect and trace back)
>
> In my opinion the power and usefulness of inserting X's to detect designer
> failure in RTL outweighs the fact that synopsys will never "create" an
> X from gates.
>
> - Paul M Gerlach
> Tektronix, Inc. Beaverton, OR
From: "Harry Foster" <foster@rsn.hp.com>
Hi, John,
I read with interest the discussion concerning X-state assignments in the
RTL design. I believe that using the X-state at the RT-level is a bad
idea -- even without the performance penalty that it causes in simulation
and equivalence checkers and the fact that pre-synthesis vs. post-synthesis
simulation runs may differ as Cliff points out. RTL simulation using the
X-state can be both excessively pessimistic and optimistic, and attempts to
over-come these shortcomings are impractical.
Consider X-state pessimism -- an arithmetic operation is one example of
gross pessimism in X-state RTL simulation.
reg [15:0] a,b,c;
...
begin
b = 16'b0000000000000000;
c = 16'b000000000000X000;
a = b + c;
$display(" a = %b",a);
end
The result for "a" in a four-state Verilog simulator will be
a = XXXXXXXXXXXXXXXX
At the cost of reduced simulation performance, a Verilog gate-level
simulation can more accurately handle this addition, resulting in
a = 000000000000X000
More insidious, however, is the way that RTL simulation of 'case' statements
and 'if-else' statements with an X-state can lead to optimistic results, and
thereby hide real start-up / initialization problems in a design.
For example, given an XX as the start-up state for "d", the "case" will
always take the "default" branch. Hence, this will only test one of the
four possible branches that the start-up condition could actually take, if
we consider the four possible two-state interpretations of the XX bits.
reg [1:0] d, e;
...
begin
case (d)
2'b00 : e = 2'b01;
2'b01 : e = 2'b11;
2'b10 : e = 2'b10;
default : e = 2'b00;
endcase
$display(" e = %b",e);
end
The result for "e" in a four-state Verilog simulator will be that "e = 00"
whenever "d" contains an X.
It is possible to code the RTL in a style which would intercept and process
X-states more accurately, moderating both the pessimism and the optimism.
For example, our case statement could be modified to intercept X-states and
propagate their affect on the result more accurately.
reg [1:0] d, e;
...
begin
case (d)
2'b00 : e = 2'b01;
2'b0X : e = 2'bX1;
2'b01 : e = 2'b11;
2'bX0 : e = 2'bXX;
2'bXX : e = 2'bXX;
2'bX1 : e = 2'bXX;
2'b10 : e = 2'b10;
2'b1X : e = 2'bX0;
2'b11 : e = 2'b00;
endcase
end
This coding style quickly becomes unmanageable for all but the simplest
examples and is prone to errors (incompleteness). In addition, we are very
quickly loosing the designer's clear functional intent to support an
irritating consequence of RTL X-state simulation.
I agree with Cliff concerning pre- vs. post-synthesis simulation
consistency. In general, an RTL coding style and set of tool directives
must be selected which insures semantic consistency between simulation,
synthesis and formal verification tools. This is a fundamental principle
of verifiable RTL design, which I call the "Faithful Semantics Principle."
- Harry Foster
Hewlett-Packard Computer Technology Lab Richardson, TX
( ESNUG 337 Item 4 ) -------------------------------------------- [11/99]
From: "Sean Atsatt" <seana@sierraimaging.com>
Subject: Better Multipliers Without Having To Buy A Pricey DesignWare Lib
Howdy John,
Some info that might be of interest to your readers.
We recently lost access to the multiplier macro's that we have been using.
We tried the basic Synopsys DesignWare multiplier, but it couldn't meet our
requirements. We took a look at buying the DesignWare library, but a year
license was absurdly expensive just to get a multiplier. We were going to
do our own Wallace tree multiplier, but I thought maybe I should check the
web first. A quick search turned up a site that automatically builds custom
VHDL or Verilog code based on your arithmetic requirements. We tried it,
downloaded, synthesized and simulated the generated code. Works great! It
took about an hour to go through the whole process. (Synopsys scripts are
provided). We obtained performance and area similar to custom macro's we
had been using. They have an automated verification tool that will verify
your function in an FPGA, but this didn't work for us. We are running an
exhaustive check on the macro's we generated. (This will take a couple of
days of CPU time, but we have that).
The project is at: http://modgen.fysel.ntnu.no/~pihl/iwlas98/
The tool is at: http://modgen.fysel.ntnu.no
If any of your other readers have experience with this tool it would be
interesting to hear about.
- Sean Atsatt
Sierra Imaging, Inc.
( ESNUG 337 Item 5 ) -------------------------------------------- [11/99]
Subject: ( ESNUG 336 #3 ) Sarcastic Replies On Xilinx's "New" Web Presence
> If you really want to see what has changed in FPGAs, then bring up
> http://www.xilinx.com/products/virtex.htm
>
> If you want to see what has changed in software, our WebFitter, then bring
> up http://www.xilinx.com/products/software/software.htm
>
> If you want to see what's new for IP Cores and reference designs, bring
> up http://www.xilinx.com/ipcenter/index.htm
>
> The meat is there John, I just don't see what your beef is about.
>
> - Ed McGettigan
> Xilinx
From: Mike Dini <mdini@dinigroup.com>
John --
I have to disagree with your view on the expanded WEB presence of Xilinx.
This additional support service from Xilinx saved me several man-seconds
of work in my last FPGA design. (About 2 mouse click's worth, I think.)
- Mike Dini
The Dini Group
---- ---- ---- ---- ---- ---- ----
From: [ Zul, The EDA Marketing Demi-God ]
Gee, John,
If you slam my company, do I get a chance at free advertising, too? :^)
(Please keep me Zul as you did in ESNUG 311.)
- [ Zul, The EDA Marketing Demi-God ]
[ Editor's Note: Actually, Zul, yes, if your company gets criticized in
ESNUG or anything else I write, it's my personal belief that you have
the right to publically reply to the criticism. It's fair. - John ]
( ESNUG 337 Item 6 ) -------------------------------------------- [11/99]
Subject: ( ESNUG 336 #10 ) Concerning The Way To Insert BIST Question
> I have question regarding Built-In Self Test (BIST). I understand that
> Design Compiler doesn't support BIST. I have to manually get LFSR and
> MISR from the DesignWare Library and then hand instantiate it my module.
> Is there a better way to do BIST that I'm not seeing?
>
> - Najib Adalat
> Infineon
From: Ron Walther <rwalther@us.ibm.com>
John,
BIST and other Design for Test insertion tools are available from several
vendors (LogicVision, Mentor, . . . ). If you're an IBM Microelectronics
customer, IBM's TestBench offers DFT insertion tools and consultation
services (http://www.chips.ibm.com:80/services/testbench/). The DFT/BIST
IP, tools and consultation services from these vendors aren't free, but
they can provide proven test solutions to speed your time to market.
- Ron Walther, an IBM DFT Consultant
IBM Austin, TX
( ESNUG 337 Item 7 ) -------------------------------------------- [11/99]
From: Gzim Derti <gderti@intrinsix.com>
Subject: Help! Gzim's Being Burned By The "is_hierarchical" Attribute!
John,
If possible could you squeeze this into this week's ESNUG???? When I read
in a hierarchial design top level and link up the design, I need to
perform a:
get_attribute find(design, <design_name>) is_hierarchical
to see if the design that I am looking at is either a structural or a leaf
module.
According to Synopsys documentation, if I perform get_attribute on a design
that consists of ONLY technology library components, the return of the
get_attribute command should be "false"... BUT I ALWAYS get "true"! I have
tried "get_attribute" on designs, cells, references and come up with the
same results. Here's a transcript of what I did and what was returned:
dc_shell> find(design, "*")
{"ref_rx_chan_fltr", "ref_fir_len95", "ref_out_if",
"ref_out_if_DW01_add_19_0", "ref_out_if_DW01_sub_19_0",
"ref_out_if_DW01_add_19_1", "ref_in_if", "ref_small_mux2",
...
"ref_multiply_193", "ref_multiply_193_DW02_mult_18_18_0"}
dc_shell> get_attribute find(design, ref_in_if) is_hierarchical
Performing get_attribute on design 'ref_in_if'.
{"true"}
I would expect "false" since when I do a current_design ref_in_if and a
report_reference I get the following:
****************************************
Report : reference
Design : ref_in_if
Version: 1999.05-4
Date : Mon Nov 15 12:19:12 1999
****************************************
Attributes:
b - black box (unknown)
bo - allows boundary optimization
d - dont_touch
mo - map_only
h - hierarchical
n - noncombinational
r - removable
s - synthetic operator
u - contains unmapped logic
Reference Library Unit Area Count Total Area Attributes
------------------------------------------------------------------------
AN210 GS30_W_125_1.65_CORE.db 1.250000 9 11.250000
AN221 GS30_W_125_1.65_CORE.db 1.750000 1 1.750000
BU130 GS30_W_125_1.65_CORE.db 1.750000 63 110.250000
...
TDP10 GS30_W_125_1.65_CORE.db 6.750000 11 74.250000 n
TDP20P GS30_W_125_1.65_CORE.db 7.000000 3 21.000000 n
TO010 GS30_W_125_1.65_CORE.db 1.750000 6 10.500000
------------------------------------------------------------------------
Total 30 references 951.750000
All of the cells are from the tech library GS30 !!! I'm stumped and REALLY
need to get past this ASAP. Thanks for any/all help.
- Gzim Derti
Intrinsix Corp. Rochester, NY
P.S. Have a Happy, Healthy, and Safe Holiday next week!!!!!
---- ---- ---- ---- ---- ---- ----
From: [ The Synopsys Support Center ]
To: Gzim Derti <gderti@intrinsix.com>
Hi Gzim,
You are right, the man pages for design attributes says that a design is
hierarchical only if it contains cells which are not leaf cells.
I found STAR 69694 filed to report the same problem. I doubt if there is
a solution to this problem but I'll let you know what the DC folks say about
this one as soon as I hear from them.
- [ The Synopsys Support Center ]
---- ---- ---- ---- ---- ---- ----
From: Gzim Derti <gderti@intrinsix.com>
To: [ The Synopsys Support Center ]
Thanks for your response, I hope the test-case stuff I sent you worked
easily. Just so you know, I REALLY need this to work for my current
synthesis flow to have ANY chance of running. Trying to work with
multiply instantiated structural blocks is IMPOSSIBLE without being able
to figure out the difference between hierarchical and non-hierarchical
designs "on the fly".......
This is how I ran into this problem. I can parse through the original
code to find the structurals, but if I need to perform a uniquify on a
structural block that will modify my structural list, I then need to be
able to decide what type of block I'm dealing with BEFORE I try and
compile multiple structural hierarchies needlessly.
ANY help would be GREATLY appreciated.
- Gzim Derti
Intrinsix Corp. Rochester, NY
( ESNUG 337 Item 8 ) -------------------------------------------- [11/99]
From: "Clifford Cummings" <cliffc@sunburst-design.com>
Subject: Cliff Trashes Navabi's New "Verilog Digital System Design" Book
John -
I know I owe you a review of the book "Logic Synthesis Using Synopsys", a
book that has earned my vote for the Most Flawed Book About Synthesis For
Over $100 -- but in the mean time, you might enjoy another review of a new
Verilog book that I did on behalf of one of my Verilog students. The book:
Zainalabedin Navabi - Verilog Digital System Design - McGraw-Hill, 1999
Four words: "It stinks; run away!"
Most of the acknowledgements in the book are for students, editors and
family. Next time, Mr. Navabi might want some actual Verilog industry
experts to review his text for accuracy and quality. Students only mimic
the professor, editors only make the content pretty, and the family only
shows patience!
It is also common courtesy to correctly spell the names of companies that
provide software to the author. The table of contents lists "F.4 Simulcad
Verilog Software." He did correctly reference the Simucad Silos3 simulator
back in section F.4.
The first two code examples in the book are not Verilog. What's the point?
Figure 1.5 shows the book's first "Verilog description". Unfortunately the
example is not Verilog, it is VHDL!
Indeed, the book appears to be a VHDL book that has been translated to
Verilog (poorly). There is a definite VHDL flavor to the book. Examples:
- The pseudo code description at the top of page 62 uses VHDL
variable assignments.
- The state machine code on page 55 is even a poor coding style
for VHDL.
- Figure 10.16 (page 298) VHDL-like verbose assignments:
ac <= 8'b00000000;
...
mar <= 12'b000000000000;
The more Verilog-like way to make these assignments is:
ac <= 8'h0;
...
mar <= 12'h0;
- The Verilog example in section D.2 (page 423) starts with a
VHDL package.
The first actual Verilog example of the book shows up on page 34. Far too
many silly diagrams and pseudo-code examples occupy the first 33 pages of
the book.
The use of nonblocking assignments in the book is inconsistent and does not
follow common recommendations. Use nonblocking assignments for sequential
logic, use blocking assignments for combinational logic. Example
sequential-code figures that do not use nonblocking assignments include:
- Figure 3.15 (page 36)
- Figure 3.17 (page 38)
- Figures 3.19, 3.27, 3.31, 3.38, 3.44, etc.
- (too many others to enumerate)
Many of the early Verilog examples emphasize Boolean equation and structural
coding styles: Figures 3.19, 3.24, 3.25, 3.38, 3.40. These descriptions are
very low-level and not very synthesis-efficient. The reader is developing
the wrong habits early in the book.
The UDP flip-flop in figure 5.15 on page 97 is wrong. Table entries are
needed to describe what happens on preset and reset transitions. Without
these entries, when reset goes to a 0, the q output will go unknown. Same
problem with the preset signal.
A full Boolean description for a bit comparator in Figure 5.24. Why? If
one is trying to design everything using gate primitives, this might be a
good reference book.
In Figure 6.8 (page 137), using a `include to include a task is pretty
silly. The task cannot be compiled separately (the task code outside of a
module would only produce syntax errors) so there is no point to keep the
task code in a separate file.
In this book, I found very few examples of case statements. I think casez
and casex were only mentioned in one paragraph on page 242. A casez
instruction would have greatly simplified the example in figure 8.9 on
page 188.
The treatment of state machines in section 8.3 is pathetic. Ignore the
coding style shown in this section. The state machine code described at
the top of page 247 and shown in Figures 9.32 and 9.34 includes an initial
block to handle the reset. This is both bad and non-synthesizable.
Initial blocks are not synthesizable and should generally only be used
inside of a testbench.
The first eight chapters are full of gates, instantiations and Boolean
equations. What happened to RTL coding? One might as well do all of the
designs using PLDs and PLD programming languages.
The "Verilog partial code" in Figure 9.41 is not Verilog code. It is a
pseudo description.
More initial blocks in the system_i module in Figure 9.43. Bad.
Non-synthesizable. And again in Figure 9.44. Even initializing signals
in a VHDL model description is a bad idea for synthesis.
RTL coding styles are almost absent from this book.
The Verilog synthesis examples in Appendix E include non-synthesizable
examples. The State machine with initial block on page 441 is one example.
Other examples are inefficiently coded.
Personal opinion -- I find the use of the IEEE-standard schematic symbols
throughout the book to be irritating and distracting.
In case there was any question, I do not recommend this book. In my
opinion, any engineer or engineering student trained using this book
will have to be re-trained before they will become proficient designers
using Verilog.
- Cliff Cummings
Sunburst Design, Inc. Beaverton, OR
( ESNUG 337 Item 9 ) -------------------------------------------- [11/99]
From: Dieter Peer <peer@iis.fhg.de>
Subject: What Are The Gotchas Concerning Using Behavior Compiler w/ FPGAs?
Hi John, and thanks for running ESNUG forum.
I would like to learn from engineers out there, who use Synopsys Behavior
Compiler (BC) for FPGA design. The problem we permanently run into is that
we target our designs primarily towards ASIC technology, but we would like
to prototype a (set of) FPGA(s), that are functionally identical to the
ASIC, running at full system speed (30 MHz).
The design flow works perfect for "normal" designs (mostly hand-written
VHDL RTL-level code). But we spend far too much time retargeting BC VHDL
code, that perfectly synthesizes for the ASIC, but usually does not fit
while using the same timing constraints with the FPGA design flow.
The question is:
Do other engineers know some "tricks", "general guidelines", or "do's and
dont's" when retargeting Synopsys Behavior Compiler Code to different
technologies?
Perhaps we would not run into these BC problems, if we did *first* target
to the slower (FPGA) technology, and *then* retarget the design to ASIC
technology. But then we might loose performance on the ASIC. Any ideas?
- Dieter Peer
Fraunhofer-Gesellschaft
( ESNUG 337 Item 10 ) ------------------------------------------- [11/99]
From: "Markus Meng" <meng.engineering@bluewin.ch>
Subject: We're Stuck Doing Our Own SpeedChart Y2K Compliance -- Any Ideas?
Some of you may still use the excellent, but dead & unsupported, SpeedChart
Tool Environment on SunOS/Solaris and HP-UX. Actually we are trying to fix
the Y2K problem found in the license daemon by a new daemon, which would
replace the old fspd but still provide the same amount of functionality
after the 31.12.1999. Any help appreciated.
- Markus Meng
Meng Engineering Baden, Germany
( ESNUG 337 Item 11 ) ------------------------------------------- [11/99]
Subject: An On-Line Tutorial On How To Synthesize SUN's picoJava Core
> Does anybody know a tutorial about the synthesis of SUN's picoJava core?
>
> - Rainer Dorsch
> University Of Stuttgart Germany
From: "Bassam Tabbara" <tbassam@eecs.berkeley.edu>
This pointer might be helpful since the picoJava core I believe comes with
synopsys synthesis scripts...
http://www.dacafe.com/DACafe/ASICCOURSE/
Ciao!
- Bassam Tabbara
U.C. Berkeley Berkeley, CA
( ESNUG 337 Item 12 ) ------------------------------------------- [11/99]
From: [ Kenny From South Park ]
Subject: Free DES Encryption/Decryption Plus Synplicity vs. FPGA_Express
John,
Check out the following web site: http://www.free-ip.com/DES/index.htm
Free DES encrytion/decryption!
Here they also compare Synplify against FPGA_Express (July 1999 version of
the tool). Synplicity is the clear winner. Notice the run times! 30
minutes in Synplify vs 6 hours in FPGA_Express.
- [ Kenny From South Park ]
( ESNUG 337 Item 13 ) ------------------------------------------- [11/99]
Subject: ( ESNUG 336 #5 ) Veritools' Undertow Can Display Raw SPICE Output
> I'm interested in any tool (shareware, commercial...) which can read in
> and display files in Raw SPICE format.
>
> - Martin Seifert
> Siemens / Infineon AG
From: Robert Schopmeyer <schop@vt3.veritools.com>
Hi, John,
Undertow, the waveform tool from Veritools, supports this format and almost
all of the other formates for analog and digital simulators including, TR0,
AC Sweep, DC Sweep, ft0, ".out", VCD, VCD with std_logic, PLI, FLI, and
".wav". Undertow can be used with almost all of the analog and digital
simulators in the market today including, HSpice, PSice, Smart Spice,
Powermill, Timemill, Railmill, Verilog XL, Verilog NC, VCS, VSS, Fintronics,
Modeltech Verilog and VHDL. It includes post processing for both analog and
digital simulations including filters, FFT, IFFT, math functions, etc, along
with a complete Perl scripting tool so users can also do any of these
complex operations as part of a Perl script. Undertow can be downloaded from
www.veritools-web.com.
- Robert Schopmeyer
Veritools, Inc.
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