[ Editor's Note: This ESNUG consists exclusively of all the e-mail
replies/corrections/strong reactions/helpful hints from sending out
the DAC'99 Trip Report out last week. Happy reading! - John ]
> As I got out of the taxi in front of my hotel and the driver handed
> me my 40 lb duffel bag -- "*HOLY-MOTHER-OF-GOD!!!*" -- my back VERY
> painfully went out. They checked me into my hotel room with the
> bellhop bringing me in on his cart. (I tipped him $15.)
From: gcorbett@cspi.com ( George Corbett )
John:
I've been a subscriber (as a lurker) to ESNUG for about 5 years and
while there have been many postings that were useful and interesting,
your account of the back pain episode is the first thing that has prompted
me to write. I have had recurring back pain ever since an episode with a
portable Tek scope (a 454, I think) some time in the late 70's. At that
time I was incapacitated for several days, and then it just "went away."
However, over the years I kept reinjuring myself from time to time, and
it always seemed to be something trivial that triggered the seizure.
Each time it happened I would start feeling a twinge, then stiffness, and
within a few hours I would be in extreme pain.
To make a long story short, over the years I've seen several kinds of
doctors (GPs, orthopedic surgeons, chiropracters) over the years, and all
that was offered to me was bed rest, painkillers, muscle relaxants,
surgery, or (in the case of the chiropracter) perpetual care by a spinal
adjuster. I heard too many horror stories about back surgery to try
that, so I did a lot of drugs.
<true_believer_testimonial mode ON>
And then... I read about a treatment called the MacKenzie Method. It
offered a plausible model for the problems I had experienced, and is
oriented toward self treatment. I did a web search, called around an
found a therapist, and tried it out. Since then (for about four years)
I have had NO episodes requiring bedrest, I have had only one incident
when I missed time from work (and only one day), and I have been largely
free of pain. All it has cost me was the initial series of training
visits to the MacKenzie practitioner, and my own regular attention to
a regimen of exercises and body mechanics.
No drugs, no surgery, no regularly scheduled visits for 'adjustment'.
There website is: http://www.mckenziemdt.org/infofor.htm
<true_believer_testimonial mode OFF>
I have a lot of sympathy for anyone suffering from back pain, and I wish
you luck.
- George Corbett
CSPI
( ESNUG 323 Subjects ) -------------------------------------------- [7/99]
Item 1: Mentor CEO Wally Rhines Gloats On Calibre / Denies Renoir Rumors
Item 2: EDA Product Keyword Counts & TeraForm Isn't A Datapath Compiler
Item 3: Gotchas If You Let Avanti Apollo P&R Restitch Your Scan Chains
Item 4: Nine Pummel Cooley For 'Big Brother Is Watching You!' Misquote :^(
Item 5: Where To Find The Whole 'Women In EDA @ DAC'99' Trip Report
Item 6: Those User DAC-NET Headaches And How To Telnet from Compaq PCs
Item 7: New Evidence Of Heavy Synopsys Involvement In Military Contracts?
Item 8: Monterey Dolphin Put 800 kgates Into 12,000 Microns, Not 1,200
Item 9: Thoughts On Intel 'Betting The Farm' On The IA-64 Transition
Item 10: CAE Plus Inc. Rebuts How Their Tool's Function Was Explained
Item 11: Uh, Actually, EDA Vendors Understand Customers Wanting Competition
Item 12: Did Anyone Get One Of Those Damn Altera Pool Cue Sticks Home ?
Item 13: You Forgot To Mention That Veritools Sells At 1/3 DeBussy's Price!
Item 14: Chinese Avanti/Mentor/Cadence User Experiences & Their View Of DAC
Item 15: HDAC's Shameless Self-Promoting Quote Of The DAC'99 Trip Report
Item 16: Synopsys ACS Will Come With Both DC Expert And DC Ultra Licenses
Item 17: OrCAD's Defends Their Big Brother Infomercial 'eCapture' Strategy
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
( ESNUG 323 Item 1 ) ---------------------------------------------- [7/99]
Subject: Mentor CEO Wally Rhines Gloats On Calibre / Denies Renoir Rumors
> The technology and integration leader at this years DAC for physical
> verification was Mentor's Calibre. They have finally taken a lead
> position in the marketplace and should not face any major competitors
> for dealing with large designs (over 500K devices) mixed hierarchy
> and mixed design methodology devices for the next 3-4 years. They
> have a number of nice integration issues with the product that make
> it very attractive -- including a standardized verification language
> that extends to PDR verbiage as well as verification code. This
> standard language is Mentor product independent -- that is their old
> tools, current tools, and new tools will read the same decks so there
> is no legacy data problem on old tech files. Additionally, they have
> run-time optimization of the run decks, which allows for multiple
> styles of run set development to still result in high performance
> verification runs. Politically, Mentor had some major coups -- they
> attracted several very high up technical people from the Avanti
> Hercules program to aid the propagation of the Calibre program.
> ( http://www.mentorg.com )
>
> - an anon engineer
From: [ Wally Rhines, CEO of Mentor Graphics ]
John,
Glad you've finally heard the good news over here at Mentor about Calibre.
As you recall, I told you about it two years ago at SNUG in San Jose. (I
recall you weren't much persuaded at the time because you didn't know what
physical verification was, so allow me the opportunity to gloat a little.)
Calibre has won corporate standardization at 19 of the world's 25 top IC
manufacturers, the majority of the world's top pure play foundries, and all
top Japanese IC companies. (That's folks like HP, AMD, LSI, VLSI, Sony,
Samsung, TI, Nokia, Motorola, Mitsubishi, Toshiba, Philips, Sun, UMC, TSMC
and a bunch more. I could go on for another couple of paragraphs of
customer names but that's probably over the top.)
According to Dataquest, Calibre captured 25.3 percent of the physical
verification market in 1997. By our own estimates (Dataquest hasn't
published for the year yet; we're looking forward to their expected August
release), the 1998 growth rate of the Calibre tool suite exceeded 200
percent, while the overall market growth for physical verification grew at
12 percent.
We're not standing still either. We just announced in June that Calibre's
next-generation technology -- the integration of Reticle Enhancement
Technologies including Optical Process Correction (OPC) and Phase Shift
Masking (PSM). We've already had success with this at Advanced Micro
Devices and Hitachi.
> "A [ Mentor ] Renoir developer told me they're being (or about to be)
> re-deployed on other products. Renoir will be placed into maintenance
> only mode. This is how it was told to me. Do I believe it? I did
> express some incredulity at the time, but EDA is a funny business. Maybe
> the bundling of MTI-Exemplar-Renoir is nothing more than a visit to the
> Last Chance Saloon." ( http://www.renoir.com )
John, I think Dr. Evil shagged you on this one. Renoir is doing very well;
we've moved to #1 market position, though we're going to have to wait on
Dataquest for the new numbers to verify that.
We saw 54 new customer wins with Renoir in Q2 (all non-academic). Big Q2
wins included that really big silicon partner of Microsoft that we can't
name, Litton Systems, Alcatel, Texas Instruments, Motorola, Marconi
Avionics, Matra Bae Dynamics and I-O Sensors Inc. Repeat orders came from
Ericsson and Nokia.
Of course, perhaps the best measure of success is that we're growing the
organization, we are currently recruiting for additional new positions in
Engineering, Documentation, QA, Technical Marketing and Marketing. Point
anybody interested our way! (Well, except Dr. Evil and Mr. Bigglesworth.)
- Wally Rhines, CEO
Mentor Graphics
( ESNUG 323 Item 2 ) ---------------------------------------------- [7/99]
Subject: EDA Product Keyword Counts & TeraForm Isn't A Datapath Compiler
> THE EMPEROR HAS NO CLOTHES? For this DAC Trip Report, I had 77 engineers
> respond. And, as a rough cut on how engineers comparitively saw all these
> new physical tools, I did a quick keyword count.
>
> Magma 'Blast Fusion' 103
> Avant! Jupiter 48
> Cadence Ambit PKS/Envisia 26
> Monterey Dolphin 22
> Synopsys 'Chip Architect' 9
> Tera Systems TeraForm 5
> Sapphire FormIT/NoiseIT/PowerIT 3
> Silicon Perspective 'First Encounter' 3
> Aristo 'IC Wizard' 2
>
> Mentally checking the data, it made sense. The between-synth-and-P&R
> tools like TeraForm, Sapphire, Encounter, and IC Wizard weren't big news
> items compared to the Magma/Monterey/Avant! stories. What surprised me
> was that so few engineers made reference to Chip Architect from Synopsys.
> Roughly a 10X difference between it and Magma.
From: Richard Gordon <rgordon@terasystems.com>
John,
(I apologize that I didn't direct my *huge* marketing staff to contact all
of our customers and DAC prospects and urge them to respond to your DAC
User Survey. I know it's a little late, but since Tera shows up 9 times
in this email, could you pump up our keyword count? <Grin>.)
I wish to clarify the misperception that our TeraForm product is squeezed
in-between synthesis and place-and-route, like X-IT, Encounter, & IC Wizard.
Since an earlier ESNUG thread (ESNUG 279, 280, 281) successfully helped to
position Tera Systems incorrectly as a DATAPATH company, which we are NOT,
perhaps you will grant me license to set the record straight -- Tera
delivers systems for RTL _design planning_.
Our TeraForm RTL design planning product is an interactive FRONT-END system
that is used PRIOR to gate-level logic synthesis. TeraForm partitions the
RTL logical hierarchy into a physical hierarchy, designed to produce an
efficient physical implementation, and constructs a detailed, full-chip
floorplan (what Gary Smith calls a silicon virtual prototype). The
floorplan gives TeraForm wiring parasitics that are used for accurate RTL
timing analyses.
TeraForm reads in RTL, works on it, and outputs RTL.
The TeraForm'ed RTL, wiring parasitics, timing, and floorplan data are
emitted as constraints for gate-level synthesis and place-and-route tools,
giving them a better starting point and accelerating timing convergence
at high clock speeds.
Hope your back is fully recovered!
- Richard Gordon, Executive VP
Tera Systems, Inc. Campbell, CA
( ESNUG 323 Item 3 ) ---------------------------------------------- [7/99]
Subject: Gotchas If You Let Avanti Apollo P&R Restitch Your Scan Chains
> "I ran into a guy named Al Crouch at the Mentor's Design-For-Test
> booth. He clued me in on a bunch of scan chain problems, so I feel
> obliged to put in a plug for his book "DFT for Digital IC's and
> Embedded Core Systems". Al definitely had a strong opinion that
> Synopsys' Test Compiler is an inferior product. (Probably why
> Mentor Graphics hosted him at their booth).
>
> Here are the scan chain gotchas he told me to watch for if we allow
> Avanti Apollo P&R to restitch the scan chain:
>
> 1) Apollo will not recognize separate clock domains when it
> restitches. It simply routes from flop to nearest flop without
> regard to the clock. To get around this you need to put each
> clock domain on a separate scan chain and explicitly tell Apollo
> which registers are on which chain. (I think that putting each
> chain on it's own enable facilitates this.)
>
> 2) We cannot allow Synopsys to put buffers along the chain. Apollo
> ignores them, routes flop to flop, and leaves the buffers and
> inverters hanging.
>
> 3) Apollo does not have any sense of timing, so when it restitches
> and routes to the flop next door it could cause hold violations.
> Al mentioned a design he had with about 5000 flops. Apollo
> introduced 3000 hold violations.
>
> Email Al_Crouch@prodigy.net w/ questions. He was a really nice guy."
>
> - an anon engineer
From: [ An Ounce Of Prevention ]
John,
I snipped this part of your trip report out and forwarded it to our P&R
guy. He was pleased to get these warnings ahead of time. Thanx!
Anon if you print this.
- [ An Ounce Of Prevention ]
( ESNUG 323 Item 4 ) ---------------------------------------------- [7/99]
Subject: Nine Pummel Cooley For 'Big Brother Is Watching You!' Misquote :^(
> BIG BROTHER INFOMERCIAL EDA In a fairly troubling new developement for
> EDA, OrCAD has announced eCapture, a free version of their schematic
> capture program -- but 'free' with a catch. It's hooked to the Internet
> and when it senses what types of parts you're placing, for example DSP
> chips, you'll suddenly see lots of paid ads for brands of DSP chips.
> Big Brother Infomercial EDA. Yeach. ( http://www.activeparts.com )
>
> "Big Brother Is Watching You!"
>
> - a motto from Aldous Huxley's book "1984"
From: Richard Gordon <rgordon@terasystems.com>
ARRRRGGGHHHH! John, you dissed one of my favorite authors, George Orwell,
who wrote "1984." Bummer! Please grovel publicly as you apologize to the
world.
Thank you. ;-)
- Richard Gordon
Tera Systems Campbell, CA
---- ---- ---- ---- ---- ---- ----
From: Mustafa Altintas <altintas@Cadence.COM>
Well, who's this Huxley? I think George Orwell is the only writer
who came up with a novel title like this...
- Mustafa Altintas
Cadence
---- ---- ---- ---- ---- ---- ----
From: Dyson Wilkes <Dyson.Wilkes@swindon.ericsson.se>
FYI
"Big Brother is Watching You!" comes from George Orwell's book '1984'.
See http://opac.lancs.ac.uk/cgi-bin/opac?1aKH+612
Huxley wrote "Brave New World" which is maybe what was in your mind?
- Dyson Wilkes
Ericsson Components Westlea, Swindon, UK
P.S. Great DAC report, thanks.
---- ---- ---- ---- ---- ---- ----
From: Richard Steedman <Richard_Steedman@pmc-sierra.com>
The quote is indeed from "1984", but "1984" was written by George Orwell.
The book by Aldous Huxley you're probably thinking of is "Brave New World".
All the best,
- Richard Steedman
PMC-Sierra
---- ---- ---- ---- ---- ---- ----
From: yaron kretchmer <yaron@lsil.com>
John-
Aldus Huxley didn't write "1984 ", it was George Orwell. However Aldus did
write a lot of neat stuff, the best, IMHO is "The doors of Perception".
Ciao,
- Yaron Kretchmer
LSI Logic Israel
---- ---- ---- ---- ---- ---- ----
From: "Frank Demarest" <frank@zygo.com>
It was George Orwell's book!
- Frank Demarest
Zygo
---- ---- ---- ---- ---- ---- ----
From: Harry Hollander <asicboy@yahoo.com>
Not to nitpick, but this is George Orwell; Huxley wrote "Brave New World".
If we let stuff like this slip, engineers might get the false label of
being focused only on their work to the exclusion of all other interests
or social interaction...
- Harry Hollander
---- ---- ---- ---- ---- ---- ----
From: [ Synopsys Tech Support ]
Jeez! John, this is a blooper if I ever saw one! "1984" was written
by George Orwell; not Aldous Huxley!!!
- [ Synopsys Tech Support ]
---- ---- ---- ---- ---- ---- ----
From: "Brett Bartleson" <Brett.Bartleson@COMPAQ.com>
Whoops John! Perhaps you've already realized, or heard about this mistake.
"Big Brother" is from George Orwell's "1984". Aldous Huxley wrote "A Brave
New World".
- Brett Bartleson
Compaq Computer
( ESNUG 323 Item 5 ) ---------------------------------------------- [7/99]
From: Peggy Aycinena <peggy@isdmag.com>
Subject: Where To Find The Whole 'Women In EDA @ DAC'99' Trip Report
John,
I, for one, loved your DAC Trip Report. If your readers to see the full
text of my article on Kathryn Kranen @ DAC'99, et al, tell them to click
on: http://www.isdmag.com/dac99/articles/article4.html
Happy reading.
- Peggy Aycinena
ISD Magazine
( ESNUG 323 Item 6 ) ---------------------------------------------- [7/99]
Subject: Those User DAC-NET Headaches And How To Telnet from Compaq PCs
> EVIL DAC-NET: The ill-fated DAC-NET. Users had a love-hate relationship
> with it. Half of DAC-NET was SUN Solaris machines and the other half
> was brower by Genedax does this too :)
- Joel Pothering
Genedax
( ESNUG 323 Item 7 ) ---------------------------------------------- [7/99]
Subject: New Evidence Of Heavy Synopsys Involvement In Military Contracts?
> WE DID NOT PRINT THAT Two weeks before DAC, Kluwer Academic sent out a
> flyer advertising various chip design books. ( http://www.wkap.nl ) The
> book "Understanding Behavioral Synthesis" by John Elliot, a Mentor
> employee, was on the cover of the Kluwer flyer. This got me curious
> because Mentor offered an interesting new behavioral synthesis tool,
> Monet, two years ago -- so I wondered if the book was about Monet or
> Behavioral Compiler from Synopsys. At the Kluwer booth at DAC, I asked
> for the book. The guy in the Kluwer booth said "Mentor bought the entire
> first edition run for its customers." I said, "That's OK. I just want
> to look at a copy of it for a minute." He replied: "Legally, all I can
> say is that Mentor bought the entire first edition run for its customers."
> Oh. So 750 copies in that first printing at $115 each, that's $86,250
> Mentor spent to hide something... Hmmmm....
From: Paul Gerlach <paulge@mdhost.cse.tek.com>
John,
Here's another humorous Kluwer story: I have in front of me that flyer for,
"17 New Books!", "Design Methodologies" that you wrote about. If you look
closely at the pictures of the front cover of 5 books, RMM, etc, one is,
"ADVANCED ASIC SHIP SYNTHESIS Using Design Compiler". (Note the 'SHIP'.)
Is Synopsys now customizing Design Compiler just for the guys on contract
to the Navy? Does Synopsys have a secret Dept. of Defence contracting
division we've never heard about?
- Paul M Gerlach
Tektronix Beaverton, OR
( ESNUG 323 Item 8 ) ---------------------------------------------- [7/99]
Subject: Monterey Dolphin Put 800 kgates Into 12,000 Microns, Not 1,200
> "Monterey: SUITE DEMO: "Dolphin"
>
> Simultaneous P&R, timing, logic optimization. ... Scan chain
> reordering to reduce congestion. Recommend: ATPG after P&R. Largest
> example: 280k cells, 800k gates, 1200 microns on a side1. 1-2 days
> run time on a multiprocessor (Sun 6500, 24 processor, 24 GByte).
> Input: .lib, netlist, lef, Synopsys timing constraints. In-memory
> data model, checkpoint capability."
>
> - an anon engineer
From: Simon Favre <simon@mondes.com>
John,
Whew! what a trip report! One minor correction: In the Monterey Design
Systems "Dolphin" section, our largest example was 12000 microns on a side,
not 1200. If we could put 800K gates in an area 1.2 millimeters on a side,
WE would be buying Cadence and Avant! The "Dolphin" section of your report
sounds a lot like my suite demo speech condensed...
Thanks for the additional perspective on DAC.
- Simon Favre
Monterey Design Systems (& former Synopsys lib manager at LSI Logic)
( ESNUG 323 Item 9 ) ---------------------------------------------- [7/99]
Subject: Thoughts On Intel 'Betting The Farm' On The IA-64 Transition
> "First CEO Speech by Paul Otellini, Exec. VP Intel. This speech was a
> not-so-vaguely disguised sales pitch for Intel IA-64 architectures and
> how it should rule the world."
From: Howard Landman <HowardL@SiTera.com>
John,
Intel has a *LOT* riding on this. It could either assure their dominance
well into the 21st century, or be the stumbling block that breaks their
hold on world PCs. Major technology transitions are tricky to pull off
smoothly. Some good examples of smoothness are Mentor (Apollo -> open
hardware), Apple (68K -> PowerPC) and Sun (68K -> Sparc). Some bad examples
are Mentor (C -> C++ "late dot oh") and Daisy (proprietary -> open hardware
killed the company -- the mutual suicide pact with Cadnetix was just icing
on the lethal cake). It'll be interesting to see how they pull it off.
The biggest risk, in my mind, is that the architecture was designed years
ago, and it's really hard to plan accurately more than a couple of years
into the future in this industry. So there may be some aspects that are a
bit "off" from the viewpoint of today's needs. For example, it may not
support the kind of intimate marriage of processor and graphics that we're
seeing in the upcoming generation of gaming platforms (like Sony's
PlayStation 2). Ask anybody making a graphics card for PCs today, and
they'll tell you their biggest problem is bandwidth to the CPU; the
overall system architecture is strangling performance, and mere CPU speed
improvement won't fix that. But Andy Grove seems aware of the system
issues, so maybe they're addressing them.
HP is also betting the farm on this one.
(Statement of possible sources of bias: I have worked for Intel and Sun,
and for Toshiba on the "Emotion Engine" of the PlayStation 2, and I own
Mentor stock.)
- Howard A. Landman
SiTera, Inc. Longmont, CO
( ESNUG 323 Item 10 ) --------------------------------------------- [7/99]
Subject: CAE Plus Inc. Rebuts How Their Tool's Function Was Explained
> Looking bass ackwards at this religious C-to-Verilog mindset, CAE Plus
> ( http://www.cae-plus.com ) offers to 1000X speed up your Verilog sim by
> translating your Verilog to C, have you debug and run 1000X faster in C,
> and then when everything's done, you translate your C back to Verilog
> again for synthesis to gates. Watch out VCS & NC-Verilog!
From: Sandhya Shardanand <sandhya@cae-plus.com>
John, thanks for mentioning us in your DAC report and we appreciate your
left-handed compliment. However...
We want to clarify what appears to be some misinterpretation of how our
tools work. We only go from logic-synthesizable Verilog into RTL-accurate
C (our trademarked term for this is "RTL-C").
Most C verification companies advocate designing in C and verifying in C,
which does not allow reuse of existing Verilog models and is a major
change to the HDL design methodology. With our new tool Afterburner, we
are letting designers continue to design in Verilog and perform high-speed
verification in C. Any design modifications are made to the Verilog,
therefore there is no need to translate the C back to Verilog.
I hope that you will post the necessary correction on ESNUG.
Just for your information, here is a brief description of our three tools
and how they work together :
1) Our design capture product, ArchGen, captures the design in a
behavioral-level, graphical event flow language, while data operations
continue to the coded in Verilog. ArchGen then synthesizes the
ArchGen model from the behavioral level into both the RTL-C and the
RTL-Verilog representations. This assures consistency between the C
and the RTL.
2) Our new verification product, Afterburner, generates RTL-C from
existing logic-synthesizable RTL-Verilog and enables the designers
to continue to capture at RTL level in Verilog but provide higher
speed C verification.
3) Our C integration tool, ASVP Builder, creates a standalone C simulator
and automates the integration of one or multiple RTL-C models with
each other and other embedded-software development tools, simulators,
test benches, co-verification environments, and/or user written C
programs or hardware models to help users put together "Application
Specific Virtual Prototypes" for system-level verification.
Our approach is an evolutionary one rather than a revolutionary one such as
those advocated by other C companies.
- Sandhya Shardanand, Marketing Manager
CAE Plus Inc.
( ESNUG 323 Item 11 ) --------------------------------------------- [7/99]
Subject: Uh, Actually, EDA Vendors Understand Customers Wanting Competition
> "... at Chronologic it took ages before people would speak in public;
> and also at Ambit it was the same. In the early days nobody wants to
> upset their other mainstream suppliers (Cadence, Synopsys, etc.) by
> basically telling them that they are way, way, way behind."
>
> - Simon Davidmann, CEO of Co-Design, who makes Superlog
From: Howard Landman <HowardL@SiTera.com>
I'm not sure that's really true. I was an Ambit beta site, and I spoke up
pretty early, both in private (even though I was limited in what I could
say) and Synopsys was more than happy to send several Very Senior People
to listen to me point out problems in their latch-based synthesis and
elsewhere. Ambit, of course, was also eager to know how their own tool
was doing.) I also spoke out in public (I was a talking head in the Ambit
booth video presentation). I never got any pushback from Synopsys for
doing this, except that they really, really didn't want me to use the
A-word in my SNUG'98 presentation. :-)
- Howard A. Landman
SiTera, Inc. Longmont, CO
( ESNUG 323 Item 12 ) --------------------------------------------- [7/99]
From: bob@fla.fujitsu.com (Bob Carragher)
Subject: Did Anyone Get One Of Those Damn Altera Pool Cue Sticks Home ?
Hello, John!
Thank you for this wonderful report. Now I don't need to actually write
my own! B-)
On a similarly wry note, I was wondering if you've heard of someone who
successfully returned with one of those silly Altera pool cues? Although
I took a relatively late plane on Friday, I did not see any behind
ticketing counters, in trash cans, etc., nor did I see them coming out
the baggage claim shute. So I'm curious about whether one of your legions
of readers actually came back with one. (I traded mine away for what
turned out to be just a cheesy pen ....)
Thanks again for the report!
- Bob Carragher
Fujitsu
( ESNUG 323 Item 13 ) --------------------------------------------- [7/99]
Subject: You Forgot To Mention That Veritools Sells At 1/3 DeBussy's Price!
> "Veritool's Undertow/IV Package http://www.veritools-web.com
>
> Many of the same features that Debussy has are present here including
> the state machine tool, source code browser, posedge/negedge source
> line analyzer, perl scripting interface, RTL and gate level schematic
> generation, and a built-in LINT tool (goodbye Avanti !)."
>
> - an anon engineer
From: Robert Schopmeyer <schop@vt3.veritools.com>
John, thanks for the post about Veritools in your news letter.
One major item however that it overlooks. While Debussey has similar
features to Undertow in that it has state diagrams and RTL schematics,
it does not have nearly as many features as the Veritools' Undertow, and
it is priced at $18,900 versus the Veritools price of $4500-$6000.00.
This makes it 3-4 times more expensive than the Veritools product.
- Robert Schopmeyer, President
Veritools, Inc.
( ESNUG 323 Item 14 ) --------------------------------------------- [7/99]
From: [ Made In Taiwan ]
Subject: Chinese Avanti/Mentor/Cadence User Experiences & Their View Of DAC
Hi, John.
I have been reading ESNUG for probably 1 - 3 years here in Taiwan. I
remembered once I wrote about AMBIT but long time ago. This time I am
writing some DAC related thoughts. Just thoughts.
(1) Distributors who Sell Tools and Being Messengers
For DAC'99, even people in Taiwan like me, heard of Magma and
Monterey. Not really from the EE Times. We heard them from
distributors. EDA tool distributors in Taiwan are eyes/ears/mouths
of us. Big brothers like Cadence, Synopsys, Avanti, Mentor have
their offices here but other EDA companies afford to have only
distributors. Our complaints, our money, go through these
distributors. And that's why they live. :-)
Every year, they go DAC and try to bring hot tools back Taiwan and
if EDA guys thought they should have Taiwan market, they qualify
a distributor and then hold some Mini-DAC here. (Simplex just had
their Mini-DAC by their distributor last week)
Lots of design houses are booming out here continuingly. We've got
foundries like TSMC, UMC so that's natural to have design houses
standing by feeding their wafers.
But very few articles mentioned these distributors. I believe there
are lots of non-US visitors in DAC but I found nothing about them.
And I strongly believe there are some stories that interest other
ESNUG readers or EE Times readers. We have EE Times, Taiwan here
and I was one of the interpretors that help translating English
articles to Chinese and then published on EE Times Taiwan. They got
some articles from our point of views published and if they can be
published back in English EE Times, that would be good. At lease
let people know we are here. :-)
(2) IC == Indians and Chinese
And that's what people used to name the IC industry now. Most EDA
companies that listened to us are funded by Chinese. Sad but
interesting. Ultima listens and adds features for us. NOVAS did
it too. And these 2 companies have almost every design house being
their customers. Avanti listens so their Apollo have over 80%
market over Cadence in Taiwan.
Most of EDA companies don't even listen to us.
That is another good topic to be focused on when doing DAC review.
There must be something driving the 'IC' phenomenon. I don't
believe that's because hiring a Chinese is cheaper. :-)
(When I said this, I wish you don't have racial prejudice. ... )
(3) Back to the Physical Part
We used Avanti Apollo and its clock tree is bad. OK, now they got
Apollo II and have better performance on CTS. But wait, that feature
cost you another. Avanti delivered a bad product and now when they
fix it up they asked for more money ??? I would rather asked for a
refund for that BAD CTS option they gave me for months. :-(
Mentor is back on road again with their Calibre and they really
listen what we need. They are hacking their codes for integrating
Calibre-STAR-RC. Again, the back annotation problem. That reminds
me of some good old days. Avanti tried to tie us with their
APOLLO+Hercules+STAR_RC. And they might lose their customers in
this way. Nobody wants to be tied and who says they will be the
top always ??
Please keep me anonymous.
- [ Made In Taiwan ]
( ESNUG 323 Item 15 ) ---------------------------------------------- [7/99]
Subject: HDAC's Shameless Self-Promoting Quote Of The DAC'99 Trip Report
> "This year I decided I would ignore the big flashy booths in the middle
> and walk around the edge. Wow, was there some interesting stuff!
> Take a look at HDAC. ( http://www.hdac.com ) I spotted their stand
> in the far corner. They do static functional RTL verification that
> does quasi model checking which seems very easy to use and appears
> to actually work (in demo, of course.) They said Tandem and Cisco
> are currently using their tool, 'Solidify'. It a different approach.
> There are no test vectors in Solidify. 0-in and friends generate test
> vectors that they feed to an internal simulator. For Solidify, you
> write 'properties' in their HPL (which is Verilog with 4 additional
> operators) to explain how your block works. (Their rule of thumb is
> 5 to 10 lines of Verilog typically translates to one 'property'. But
> the specific metric they gave was one 12 kgate block, 8100 lines RTL
> Verilog, had used 156 'properties' -- each 'property' covered 52 lines
> of Verilog.) Then you use Solidify own 'properties'-oriented code
> coverage utility to find what you're missing. Coverage is a separate
> analysis, so it doesn't load down the tool, and it does incrementals.
> It then lets you write new 'properties' to cover what you missed.
> Currently, it's block level only with a 25 kgate per block capacity.
> I liked what I saw. I cannot comment on the tool hands-on as yet,
> but I'll keep you informed."
>
> - an anon engineer
From: "Graham Bell" <gbell@hdac.com>
John,
I shamelessly put the quote about HDAC from your DAC'99 Trip Report on
our web-site at http://www.hdac.com/cooleyda.htm and gave a hyperlink
to http://www.deepchip.com .
Thanks for the quote!
- Graham Bell, Marketing Director
HDAC, Inc. Alameda, CA
( ESNUG 323 Item 16 ) --------------------------------------------- [7/99]
Subject: Synopsys ACS Will Come With Both DC Expert And DC Ultra Licenses
> "b) Automatic synth and distributed process runs. Synopsys ACS is
> here. It looks to be viable. It does distribution to multiple
> machines (using multiple licenses of course; they all do). It only
> comes with an ultra license. The Synopsys offering is a bit further
> along and changable by the user. Ambit's offering is free, has
> more distributed stuff (like a very cool job status and control
> center), has the push button approach, but is less configurable.
> Both tools have nice stop, check and restart features. Both are
> hungry to get these working on big designs. We need a multi
> license, multi server environment to take advantage of the features.
>
> - an anon engineer
From: [ Synopsys ACS Marketing ]
Hi John,
I enjoyed reading your DAC'99 Trip Report. As always it has a lot of
interesting designers views and perspectives. I did spot in it a couple
of misunderstandings regarding Synopsys' Automated Chip Synthesis (ACS)
which I would like to correct for your readers:
1. There is no extra charge for ACS. It will be rolled out in both
DC Expert and DC Ultra.
2. The user can take advantage of ACS even when using a single server
environment. In addition to distributed compilation which requires
multiple CPUs, ACS automates the following tasks regardless of the
number of CPUs you are using: budgeting the synthesized modules,
creating the compile scripts to meet the synthesis targets for each
module, and manage the design data.
All of which can be very tedious, error prone and time consuming when
dealing with large designs.
Thanks for letting me clear this up.
- [ Synopsys ACS Marketing ]
( ESNUG 323 Item 17 ) --------------------------------------------- [7/99]
Subject: OrCAD's Defends Their Big Brother Infomercial 'eCapture' Strategy
> BIG BROTHER INFOMERCIAL EDA In a fairly troubling new developement for
> EDA, OrCAD has announced eCapture, a free version of their schematic
> capture program -- but 'free' with a catch. It's hooked to the Internet
> and when it senses what types of parts you're placing, for example DSP
> chips, you'll suddenly see lots of paid ads for brands of DSP chips.
> Big Brother Infomercial EDA. Yeach. ( http://www.activeparts.com )
>
> "Big Brother Is Watching You!"
>
> - a motto from Aldous Huxley's book "1984"
From: Jim Plymale <Jim.Plymale@orcad.com>
Hi John -
The basic problem we're trying to solve is to help the PCB designer go as
quickly as possible from the component information that's out there on the
web from manufacturers and distributors, into the schematics that they use
to document their designs, and out into partlists that they can use to
order the parts for their prototypes.
Today, the engineers use "known good components", i.e. components that have
been used before and are known to the company. There are a number of
Component Information Systems (including one from OrCAD):
http://www.partminer.com http://www.unique-technologies.com
http://www.netbuy.com http://www.wyle.com
http://www.questlink.com http://www.digikey.com
http://www.insight-electronics.com
Now let's say, you finally find the part you want and you're ready to
"design it in" -- now you have to either track down or create the schematic
symbol, and manually enter all the data that you cared about, and link it
to PCB footprints, simulation models, etc. Also, you better make copies of
the spec sheets, pricing, etc.
We thought: "So how come you can look at the part, but you can't just drag
it into your design and get links to all that information that's on the
web?" So rather than try to go out and form a standards committee and
convince all the parts manufacturers and distributors that they should
publish data in a universal format (a noble, but unlikely goal), we decided
to do the "grunt work" of linking the data freely available on the Internet
(manufacturer's part numbers, descriptions, datasheets, pricing, and
availability) to the data that OrCAD had (tons of schematic symbols, and a
bunch of PCB footprints and PSpice models) in eCapture.
We currently have data for over a half million parts from over 500
manufacturers and we're shooting for over a million by the end of the year.
O.K., so we announced that we're giving away access to all this data to
OrCAD users, and we're even providing a free application (eCapture) so
non-OrCAD users can take advantage. What's the catch? When you drag a
component from activeparts.com into your design, we keep track of it. We
use that information to build a profile. These profiles have the same
intent as the cards you fill out when you subscribe to magazines to receive
a FREE subscription. They make it possible for our sponsors (primarily
component manufacturers and their suppliers) to display messages specific
to you about stuff they think you need to know about. Seminars, white
papers, new spec sheets, reference designs, etc.
What about your Big Brother privacy concerns? None of the information will
be disclosed to suppliers unless you choose to disclose it to them. We'll
have (when the site goes live) a detailed disclosure of exactly how we
intend to use the information we collect. We understand that the data
we're collecting is highly sensitive and we intend to protect it. We're
working with Arthur Andersen (Internet & security consultants) and Trust-e
(http://www.trust-e.com) to ensure this.
Thanks for keeping us honest, John!
- Jim Plymale, VP of Marketing
OrCAD, Inc.
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