Editor's Note: When I returned from the post office last Friday (April 15th)
after mailing a horrendeous check to the government for them to use as play
money, I noticed that the sheep had been sheared earlier when I wasn't home.
(Shearing is done by professionals who schedule their appointments in units
of months. That is, they tell you they'll see you "sometime in late
March / early April.") I got a good chuckle out of seeing these now quite
embarrassed animals skittishly wandering in the back pasture and even more
of a laugh when I realized that we had all been fleeced on the same day!
- John Cooley
the ESNUG guy
( ESNUG 186 Item 1 ) ---------------------------------------------- [4/94]
From: guy_harriman@engtwomac.SynOptics.COM (Guy Harriman)
Subject: Test Compiler, TI ASICs & The Synopsys Corporate Consulting Racket
John,
It was good to meet you in person at SNUG'94. I think you are providing a
great service to the user community! I'm writing because you asked me to
write up a summary of my experiences with the Test Compiler. The reason for
doing this is to avoid other users having to repeat my experiences, and
hopefully save them some time.
In the ASIC I was designing at the end of last year, I was using TI as a
foundry. They have a technique for allowing thorough testing of embedded RAMs
called PMT (parallel module test). This works by multiplexing the internal
ports of the embedded rams directly to the IO pins of the ASIC, while
tri-stating off all the output drivers. Therefore the designer has the
freedom to connect RAM inputs to output pins when PMT is enabled.
This technique is very powerful, as it allows very good coverage of the
embedded RAMs. In my case, I used a JTAG test register to select one of five
RAMs at a time, and generated my own vectors for the RAMs (modified true and
inverse address-is-data, growing 1's, and walking 0's) with 55k vectors in
total.
The problem I had with Test Compiler was that the PMT multiplexing function
confused it, causing 3.0a and 3.0b to fatal. I talked to people at TI and
Synopsys, and it turned out that the problem was that the PMT multiplexing
macros (TP0xx) were not functionally modeled in the Synopsys libraries. I had
to write my own Verilog equivalents, and generate .db files for them. I raised
this as an issue for TI and Synopsys to work on, and they committed to provide
them. The TI synopsys libraries should model the PMT macros in a future
release.
With 3.0c, I was able to generate ATPG vectors without having a fatal.
Previously, I was told at one point that we would have to pay for a Synopsys
Corporate Consultant to look at our design at a mere $250.00 an hour.
After he came and looked at our problem he realized that the problem was on
their side, and we did not pay for the consultant. We weren't too happy with
this form of support because it adds to the cost of maintenance of the tools,
and is a hidden cost at the time of purchase.
Another problem, which other ESNUG users have also seen, is with scan
insertion in a design which already has pads present. Test Compiler will
only add the scan ports to the top level port list. Here is a fragment of
the script which reconnected the scan I/O (I had 8 scan paths):
/* Move port scanIn down to pads. */
a = all_connected(scanIn1)
b = all_connected(a)
c = all_connected(link_din_i[0])
d = b + c
disconnect_net -all a
disconnect_net -all link_din_i[0]
connect_net link_din_i[0] d
remove_port scanIn1
all_connected(link_din_i[0])
a = all_connected(scanIn2)
...
/* Move port scanOut down to pads. */
a = all_connected(scanOut1)
b = all_connected(a)
c = all_connected(pads/scanOut0)
d = b + {"pads/scanOut0"}
disconnect_net -all a
disconnect_net -all c
connect_net a d
remove_port scanOut1
all_connected a
...
This method works, but it is tedious to set up.
I also had to write a perl script to edit the final TI format TDL ATPG
vectors, as the bidirectional bus was not correctly handled by the Test
Compiler. After doing that, the ATPG vectors ran OK on the silicon, which
came out of fab at the end of January.
Overall, I took about a month longer for ATPG than I was expecting due to
these problems. Our Synopsys FAE was very good at following up on the issues,
and Synopsys and TI were both helpful in resolving the problems (we just
differed with Synopsys on who was supposed to pay for support once we
actually needed it.) Test Compiler still seems immature to me, but this is
to be expected at this stage of its development.
- Guy Harriman
SynOptics ATM group
P.S. We just bought Mentor (Checklogic) fastscan. I was able to insert scan
and get vectors in 1 day with a new design, compared with 2 months in the
Synopsys Test Compiler last time! It runs in 3 minutes compared to the 4 hours
for Test Compiler.
( ESNUG 186 Item 2 ) ---------------------------------------------- [4/94]
From: taub@corp.cirrus.com (Ed Taub)
Subject: (ESNUG Post 184 #4 185 #2) Getting Clean Verilog Out & Opus
John,
One note on Opus importing of Synopsys Verilog netlist to get schematics: at
least for backslashes, there is a push button on the Opus Verilog-import
pop-up menu called "map escaped names." This will automagically rename
signals containing backslashes into unique (i.e. mapped) signals without
backslashes. The behavioral assign & tri comments are still relevant.
Thanks to Rob Brashears (Cadence AE) for this tip.
- Ed Taub
Cirrus
( ESNUG 186 Item 3 ) ---------------------------------------------- [4/94]
Subject: (ESNUG 185 #3) Synopsys Name-based Module Instantiation Error
>John, I found a Synopsys/Verilog inconsistency that I thought you should be
>aware of, if you are not already. In name-based module instantiation Cadence
>and OVI specify that unconnected module ports are identified by empty
>parentheses as in the following:
>
> ALPHA instance1 (.Out(topB),.In1(topA),.In2());
> ^^^^^
>Synopsys generates an error with this syntax and states in their manual that
>"omitted terminals indicate that the corresponding port on the module is
>unconnected". Verilog-XL will not accept the omitted terminal syntax and
>generates a "too few module port connections" error.
---- ---- ---- ----
From: halbert@emc.com (Neil Halbert)
John, the user can just substitute some string for the (), say "null" by
piping the Verilog through the following sed script (instead of doing the
involved solution to get Design Compiler to do the right thing):
sed 's/(null)/g' file.v > filenew.v
creating (in terms of the user's original example):
ALPHA instance1 (.Out(topB),.In1(topA),.In2(null));
^^^^^^
This seems to work for the test case I created. I would read in without any
errors and didn't add additional "stuff" to the design.
- Neil Halbert
EMC Corporation
---- ---- ---- ----
From: shalom@msil.sps.mot.com (Shalom Bresticker)
Just for the record:
Omitted terminals are legal in both OVI LRM 1.0 and in Cadence Verilog-XL.
The above example appears in section 12.4.4 of the OVI LRM 1.0 and the Cadence
Verilog-XL 1.6b LRM. The sentence immediately preceding the example says,
"There could be other unused ports not mentioned in the instantiation."
The "Warning! Too few module port connections [Verilog-TFMPC]" message from
the Cadence Verilog-XL compiler is, as it states, a WARNING, not an error.
This warning was added in version 1.6c or 1.7 of Verilog-XL. The warning
can be turned off, but for users who do not generally write Verilog this way,
the warning indicates that you may have forgotten a port.
In our company, we use the omitted terminal form in both Synopsys and Verilog
extensively. For many users, this is a better workaround than position-based
notation. It gives you the advantages of name-based notation (position
independence, explicit internal/external name correspondence), without
cluttering the instantiation statement without unused port names -- which may
be numerous. (This has no connection with the requirement that Synopsys
should accept the "empty parentheses" syntax.)
- Shalom A. Bresticker
Motorola Semiconductor Israel, Ltd.
( ESNUG 186 Item 4 ) ---------------------------------------------- [4/94]
From: kenr@storage.tandem.com (Ken Rose)
Subject: Interactions Between Ungroup, Test-Compiler, and LSI Logic Format
John,
I just ran into this funny interaction, and thought I would pass it along
to you in case it saves somebody else some time.
In quick summary, the new name Synopsys gives to a cell after ungrouping uses
a separator that causes LSI to think the level of hierarchy is still there.
So if you use Test-Compiler to create scan vectors, they won't run in the
LSI environment if any sequential cells have been ungrouped.
This is what happens:
1) when you ungroup, the default naming style for new cells is:
cell_being_ungrouped/old_cell_name[number]
2) Test-Compiler will use the name of sequential cells for the BPAT vectors
in which it preloads the sequential elements, and for the VPATS001
expected output file.
3) The "/" character denotes a level of hierarchy in the LSI NDL (Net
Descriptor Language)
These three facts conspire together to produce an output that CMDE cannot run.
When the CMDE simulator looks for the BPAT cells, if any of them are ungrouped
hierarchical cells it cannot find them because the "/" separator makes it
think the hierarchy is still in the design (even though it is gone).
As a workaround, you can use the -simple_names option (see the ungroup command
in the Command Reference Manual). This causes the cell to be elevated without
changing its name. It might also be possible to use the naming rules for
this, but I haven't tried anything along those lines.
- Ken Rose
Tandem Computers
( ESNUG 186 Item 5 ) ---------------------------------------------- [4/94]
From: [ Synopsys Product Assurance ]
Subject: Corrupt VHDL Simulation File In V3.1a For IBM RS6000's
John,
There's a platform specific problem with the VHDL System Simulation release
v3.1a. The main visible symption is a lot of error messages are generated
about undefined symbols while linking CLI or LAI models to vhdlsim.
A patch tape to fix a corrupt file on the v3.1a release tape is being shipped
to all IBM platform customers -- users should make sure their SysAdmin people
install this patch. This patch is an archived library used for dynamically
linking the CLI and LAI models. You need to replace the existing libvhdlsim.a
file for v3.1a in the directory $SYNOPSYS/rs6000/sim/lib/libvhdlsim.a with
the new libvhdlsim.a file from the tape supplied by Synopsys.
All known IBM platorm VSS customers should have this patch around April 19th.
- [ Synopsys Product Assurance ]
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