Now I know why most people want to be regular W-2 employees instead of
consultants -- it's not the illusion of security -- it's to avoid all
the incredible headaches filing as an independant consultant entails!
Aaaaaaargh! You want me to help get your ASIC design project back on
track and train your team in how to best use EDA tools? Sure! No problem.
You want me to help check your company's accounting? See me run screaming
from the room! Figuring taxes makes even problematic ASIC design look
like child's play. (Now where did I put that extension form...)
- John Cooley, Just plain old 1040 (long) plus
Schedules C & SE plus Form 4868... I think.
( ESNUG 185 Item 1 ) ---------------------------------------------- [4/94]
Subject: (ESNUG 183 #1) Model Tech / Synopsys VHDL Differences
>In regards to ESNUG 183 #1, I have done a lot of comparisons between Model
>Tech and Synopsys. In addition to the items listed by Robert Hunter, I have
>found that Model Tech does not support an SDF file. Of course, this is not
>necessary for a behavioral or RTL simulation but is essential for accurate
>gate level simulation. Fortunately, I understand that they are working on an
>SDF reader now.
From: [ Name Withheld ]
John, please sign me anonymous - no name, no company, no location
A couple of more points to make...
1. The user interface on Model Tech is very friendly; new users are able to
come up to speed very fast.
2. As far as I have been told, Model Tech's SDF reader is being alpha-sited.
Not sure when it is available for general consumption.
3. The only snags so far with using Model Tech gate-level VHDL simulation is
the trial and error in getting the appropriate vhdlout variables set from
Synopsys Design Compiler. Synopsys Design Compiler documentation (on-line
and printed) in general, and in particular of the vhdlio variables leave,
in my opinion, a lot to the imagination....
4. Model Tech is generally is much more responsive than the Synopsys Design
Compiler people - have no idea if this would be different if the questions
were related to the Synopsys simulator. Without ESNUG, we would be up the
proverbial creek without a paddle.
- [ Name Withheld ]
( ESNUG 185 Item 2 ) ---------------------------------------------- [4/94]
Subject: (ESNUG 184 #4) Getting Clean Verilog Out Of Synopsys
From: fdme@sh.bel.alcatel.be (Frank De Meersman)
Hi John,
Since we are using the verilog netlist that comes out of Synopsys to generate
a Cadence Opus schematic, we had to generate a verilog netlist that did not
contain any 'special characters', such as back slahses, weird '<>' characters
used in the synthetic modules, and last but not least the 'tri', tran, and
assign statements. These statements are all considered behavioral statements
and are completely ignored by the PLI interface and also the verilog import
in Opus.
Now, here 's what we did:
We are using the same variables originally described in ESNUG 184 #4 (i.e.
verilogout_no_tri, and compile_fix_multiple_output_ports) plus I am also
using a library that contains the strap cells to Power and Ground.
So until now, this is all the same as what's decribed in ESNUG 184 #4.
But to get rid of all kinds of special characters ( backslahes, <> etc),
we are using the change_names command. I have defined the following rule :
define_name_rules opus -reserved_words {"disable", "abs", "access", "after", \
"alias", "all", "and", "architecture", "array", "assert", "attribute", \
"begin", "block", "body", "buffer", "bus", "case", "component", \
"configuration", "constant", "disconnect", "downto", "else", "elsif",
"end", "entity", "exit", "file", "for", "function", "generate", "generic", \
"guarded", "if", "in", "inout", "is", "label", "library", "linkage", \
"loop", "map", "mod", "nand", "new", "next", "nor", "not", "null", "of", \
"on", "open", "or", "others", "out", "package", "port", "procedure", \
"process", "range", "record", "register", "rem", "report", "return", \
"select", "severity", "signal", "subtype", "then", "to", "transport", \
"type", "units", "until", "use", "variable", "wait", "when", "while", \
"with", "xor"} \
-allowed "A-Z a-z _ 0-9 " -first_restricted "0-9 _" -last_restricted "_" \
-case_insensitive -collapse_name_space -replacement_char "x"
So, when I execute the command:
change_names -rules opus -h -verbose
all special characters are replaced by 'x'.
Typically we do this before we write out any db file or any report. With this
we are sure that the names in the Synopsys db, are the same as the ones in the
Verilog netlist, so the same as the ones in the Opus schematic, so the same
as the ones that we use to go to Dracula for verification.
We just have problems with the \#UNCONNECTED that Synopsys is using to
determine floating outputs, though...
- Frank De Meersman
Alcatel
---- ---- ----
From: arvind@adaptec.com (Arvind Venkateswaran)
John,
Here are a couple of ways of removing those irritating backslashes from a
Synopsys generated gate-level Verilog netlist. These escape characters have
a habit of interfering with transfer to other tools and back-annotation.
Scenario 1
----------
Before reading in your design into Design Compiler, make sure to
set the 'read_array_naming_style = %s_%d' in the .synopsys_dc.setup
file. The default value for the variable is '%s[%d]'.
With the above setting, port A[0] is changed to A_1. As a result, there
are no backslashes appearing as escape characters in the Verilog netlist.
Scenario 2
----------
If you already have a compiled design, but forgot to set the 'read_array_
naming_style' variable to the reqd. value. Obviously, you dont want to
re-compile the design just for a format change. At this point, it is too late
to set the 'read_array_naming_style' variable as it works only when the
unmapped design is being read in. Fear not, you can still avoid the escape
characters by doing the following:
1. Read in your design description or compiled .db file.
2. Set current_design to required level.
3. define_name_rules replace_left -restricted "[" -replacement_char "_"
4. define_name_rules remove_right -restricted "]" -replacement_char " "
5. change_names replace_left
6. change_names remove_right
7. write out Verilog netlist
- Arvind Venkateswaran
Adaptec Inc.
( ESNUG 185 Item 3 ) ---------------------------------------------- [4/94]
From: paulr@vail.is.brooktree.com (Paul J Rutigliano)
Subject: Synopsys Name-based Module Instantiation Error
John, I found a Synopsys/Verilog inconsistency that I thought you should be
aware of, if you are not already. In name-based module instantiation Cadence
and OVI specify that unconnected module ports are identified by empty
parentheses as in the following:
ALPHA instance1 (.Out(topB),.In1(topA),.In2());
^^^^^
Synopsys generates an error with this syntax and states in their manual that
"omitted terminals indicate that the corresponding port on the module is
unconnected". Verilog-XL will not accept the omitted terminal syntax and
generates a "too few module port connections" error.
The only work around appears to be to use position-based module instantiation.
- Paul J. Rutigliano
Brooktree Corporation
---- ---- ----
From: [ The Synopsys Hotline ]
Paul, This is a problem that was recently filed as star #18622 as a bug. The
reason is that neither we nor Cadence support the complete Verilog language.
What Cadence can read in, and what Synopsys can read in are both legal Verilog
syntax options, but in this case the tools read in different subsets of the
same language, causing a compatibility problem. So Synopsys has plans to fix
it at some point in the future, in the meantime, position-based notation is
the best workaround.
- [ Synopsys Support Center ]
( ESNUG 185 Item 4 ) ---------------------------------------------- [4/94]
From: Ron Mehler
Subject: An Unapproved Scan Methodology That Works
John, since I'm a contractor please keep my e-mail address and where I'm at
out of this but do feel free to put my name on this.
My design has many clocks, or signals that are used to gate flipflops. Some of
them are internally-generated divided clocks, others are internally-generated
who-knows-what. There are also three clocks coming in from the outside world.
The methodology I outline here violates the Synopsys guidelines but work.
To get scan into this thing, I brought clock signals up to the top level by
creating ports (both input and output) at each level of hierarchy for each
clock signal; breaking the source of the clock from its destination. This was
also done for soft reset signals, to prevent Test Compiler from deciding they
were clocks. (When TC decides reset is a clock, which it does when it traces a
clocked signals back through a Q output to the reset port of the driving flop,
it concludes that all flipflops on the reset line are always asynchronously
set/reset, and refuses to insert scan anywhere. This bug is supposed to be
fixed in release 3.1 -- but I'll believe it when I see it.)
Then each of these derived clock signals appeard to Test Compiler like an
acceptable clock, and it would insert scan. After scan is inserted, the
input/output pairs must be connected together, but at a higher level of
hierarchy, so that scan/ATPG does not see that they are really the same
signal. Since the names of each clock also change with each module, I wrote
scripts to find each flipflop and
1: set_scan false on each one
2: find its clock net name
3: compare it with a list of all the signals used as clocks
4: put the flop into the appropriate chain
5: set_scan true for each flop that was found to have an
acceptable clock
6: leave scan false for those few flops that were clocked off
some unacceptable signal
- Ron Mehler
( ESNUG 185 Item 5 ) ---------------------------------------------- [4/94]
From: [ Anonymous ]
Subject: Seeking Quickturn Emulation Horror/Success Stories
Hi John: Please keep my company and my name out of ESNUG.
I am responsible for the emulation phase of a large scale design featuring
several LSI 300K ASICS. Due to the complexity, the quantity of ASIC slices on
the board (up to 26 instances), and the risks of having to spin one chip after
another, we have chosen to emulate our designs using QUICKTURN Design's MARS
system. My question, does anyone out there validate their designs using
Quickturn, or any alternate emulation techniques and if so, have you found
any specific problems in ICE (In-Circuit Emulation) that might affect how we
generate our Synopsys output?
I think this is a relevant question since the methodology is directly affected
by the quality of the Synopsys output. For reference, we are HDL based using
the Cadence Framework for design capture. Thanks in advance for your help.
- [ Anonymous ]
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