( ESNUG 516 Item 2 ) -------------------------------------------- [12/13/12]
Subject: more Cadence follow-up to questions on the IBM 14 nm tape-outs
> What's lacking in the IBM 14 nm tapeout announcement is what parts
> of the flows were Cadence and what parts were IBM EDA. The two
> companies have a 10+ year joint EDA tool developement agreement
> together. It's from the early Cadence Catena days.
>
> - from http://www.deepchip.com/items/0514-08.html
From: [ Wei Lii Tan of Cadence ]
Hi, John,
Some of your reader "snarkies" had technical questions about which tools
were used in the Cadence-ARM-IBM 14nm tapeout. Here's our follow-up.
The front-end design was done with Cadence tools. We used RTL Compiler
with an automatic scripted flow for synthesis, and Encounter Test for
scan insertion. Conformal LEC was used for equivalence checking. All
the libraries (physical, timing, and power) were developed by ARM and
fully supported by all the Cadence tools in our RTL-to-Signoff flow.
The back-end design work was done using Encounter Digital (EDI System),
after significant enhancements were made to Nanoroute to support complex
14 nm design rules and different routing approaches.
Cadence QRC for extraction, and Encounter Power System (EPS) including rail
analysis. Cadence PVS was not used in this project.
---- ---- ---- ---- ---- ---- ----
> Does this mean that IBM has certified Cadence ETS for signoff
> and final golden signoff?
>
> Was Cadence ETS used alone? Or with EinsTimer/EinsStat and/or
> PrimeTime? How does ETS data correlate with PrimeTime? What
> about early timing estimator rules and nonlinear delay models?
> What about noise coupling? SI?
Timing & power closure, as well as final signoff, were performed using the
Cadence Encounter Timing System (ETS). Neither the in-house IBM EinsTimer
nor Synopsys PrimeTime timing analysis tools were involved in these
Cadence/ARM/IBM 14 nm tape-outs.
For the record, Cadence ETS is being used by big names like ST:
"The Cadence signoff solution cut weeks off our development
schedule. In one 24-hour period, for instance, we were able
to fix thousands of hold violations across more than 60
mode-corner combinations on this design, which contained more
than 20 million cells -- something that would have taken us
weeks to close with our prior signoff technology."
- Thierry Bauchon of STMicroelectronics (10/09/12)
For 2012 alone, there are also other press releases on the Cadence web site
from companies like CSR, ITRI, Renesas, Sharp, Fujistsu, Ambarella, and
Netronome all using Cadence ETS technology.
- Wei Lii Tan
Cadence Design Systems San Jose, CA
---- ---- ---- ---- ---- ---- ----
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