( ESNUG 514 Item 8 ) -------------------------------------------- [11/16/12]
Subject: Reader Snarkies on IBM 14 nm, Intel 14 nm, AMIQ DVT, Calibre PERC
Editor's Note: Almost every time I publish, readers send me these
concise emails that are sometimes insightful, but are more often
cynical; which is why I call them "snarkies". Enjoy. - John
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The engineers at IBM had just taped out a chip in IBM FinFET 14 nm with
an ARM Cortex-M0 processor, some SRAMs, and a mess of ARM/Artisan logic,
using Cadence Encounter Digital and Virtuoso. ...
And Cadence ETS was used by itself for all intermediate timing plus for
the final chip sign-off.
  
That last part of Cadence-ETS-only was quite interesting given a decade+
stranglehold Synopsys PrimeTime has in all things timing. I wonder what
Aart's thinking. "Did anyone else sense a tremor in the Force today?"
- from http://www.deepchip.com/items/0513-08.html
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Look! It's Daarth Vaader!
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Daarth de Geus
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"Come over to the Daarth Side, Cooley!"
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Daarth Vader!
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you should have photoshopped aart's face onto darth's helmet
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Daarth
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The Evil Empire always wins.
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Daaaaaaaaaaaaaaaart!!!!!! (He is your father, Cooley.)
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Daart de Geus. Feel the Farce.
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It'll take more than one test 14 nm IBM tapeout for the whole
STA and SSTA market to change. Too many companies have 100's
of thousands of man-hours invested in PrimeTime-based scripts
to think of changing.
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Does this mean that IBM has certified Cadence ETS for signoff
and final golden signoff?
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Was Cadence ETS used alone? Or with EinsTimer/EinsStat and/or
PrimeTime? How does ETS data correlate with PrimeTime? What
about early timing estimator rules and nonlinear delay models?
What about noise coupling? SI?
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> They also gave Cadence tools a good workout in 14 nm, too. For example
> all the std cells were made in Virtuoso. Then Encounter Digital was used
> to layout the entire design using all sorts whizbang FinFET 14 nm special
> stuff like double patterning, etc. plus built-in Cadence QRC Extraction.
>
> - from http://www.deepchip.com/items/0513-08.html
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What's lacking in the IBM 14 nm tapeout announcement is what parts
of the flows were Cadence and what parts were IBM EDA. The two
companies have a 10+ year joint EDA tool developement agreement
together. It's from the early Cadence Catena days.
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John, as IBM et al are doing this on SOI, are you aware of any
SOI-related specificities?
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If you get more actual data on these tapeouts, please publish.
We want to know more.
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Did any of the IBM 14 nm test chips go to silicon?
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I asked some Mentor contacts why the Cadence 14 nm press release
lacked DRC/LVS mentions. Although they did not outright say
it, they implied it was because the IBM 14 nm DRC/LVS runs were
done with Calibre.
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> This is big news because it's the first public non-Intel 14 nm chip.
>
> - from http://www.deepchip.com/items/0513-08.html
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My Synopsys sales guys says that the Intel 14 nm was done in ICC.
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FYI, our SNPS FAE claims they did the first 14 nm Intel tape-out.
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SNPS sources tell me 14 nm Broadwell was taped out by a joint
Synopsys-Intel team in early June. Perlmutter was to showcase it
at IDF'12 but their present process doesn't fab reliably.
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> AMIQ DVT supports Specman "e", SV, Verilog, VHDL simultaneously
> http://www.deepchip.com/look/see121101-01.html
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Do you do any fact checking on your advertisers, John?
Specman "e" <-> SV <-> Verilog <-> VHDL xlation not possible.
Too many constructs do not convert.
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AMIQ DVT claims go beyond what's doable for all HDLs.
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Do you know of any AMIQ users of this tool? My verification
guys would like to feed DVT some Specman "e" to see what
kind of messed up Verilog it spits out.
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> An on-demand Mentor Calibre PERC reliability and power webinar
> http://www.deepchip.com/look/see121101-03.html
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That PERC webinar dates from 2011. You might want to tell
the Mentor people to update it. 2013 is 6 weeks away! :)
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Is there a current PERC tutorial available? This is from 2011.
I have to do a first cut eval of it vs. Apache PathFinder.
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