( ESNUG 460 Item 7 ) -------------------------------------------- [01/11/07]
Subject: Keywords -- known and unknown Synopsys commands (score 12,412)
COMMANDS: See http://www.deepchip.com/items/0460-04.html if you want to
understand how these stats are done. Or if you want custom data.
This string hopefully finds all Synopsys command searches to DeepChip.com.
string: _
external Google search keywords
set_multicycle_path 92
create_generated_clock 91
set_max_delay 90
set_false_path 75
synopsys translate_off 64
set_input_delay 54
set_max_transition 52
synopsys infer_mux 41
set_output_delay 41
foreach_in_collection 38
slew_derate_from_library 38
hdlin_enable_presto 35
create_clock 34
set_case_analysis 33
positive_unate 31
delay_mode_unit 29
text_file_delta failed create_version operation 29
sc_uint 29
set_driving_cell 29
shm_probe 29
set_clock_latency 28
synopsys sync_set_reset 27
lvs_bscan_cells 26
sdf_cond 25
remove_from_collection 24
insert_clock_gating 24
set_scan_path 24
set_test_hold 23
max_transition 22
report_timing 22
set_dont_touch_network 22
change_names 21
primetime get_attribute 21
set_max_fanout 21
dc_shell-t 20
damem_declare 20
neg_tchk 20
primetime report_timing 19
set_ideal_network 19
synopsys parallel_case 19
set_operating_conditions 18
timing_remove_clock_reconvergence_pessimism 18
interface_timing 17
set_fix_hold 17
set_dont_touch 17
set_critical_range 16
tcl foreach_in_collection 16
dw_prefer_mc_inside 16
dc_shell script 16
filter_collection 16
set_critical_range 16
dc_shell script 16
set_scan_configuration 16
dw_prefer_mc_inside 16
dont_touch 16
set_clock_gating_check 15
transform_csa 15
hdlin_ff_always_sync_set_reset 15
get_timing_paths 15
non_unate 15
$shm_probe 14
make_cdb 14
set_wire_load 14
get_ports 14
synopsys change_names 13
set_ideal_net 13
synopsys map_to_module 13
set_clock_transition 13
set_drive 13
compile_ultra 12
sync_set_reset 12
timing_sense 12
dc_shell xg mode 12
.synopsys_dc.setup 12
synopsys full_case 12
get_alternative_lib_cells 12
report_analysis_coverage 12
synopsys_translate_off 12
high_fanout_net_threshold 12
set_timing_derate 12
negative_unate 12
fanout_length 12
.synopsys_pt.setup 12
sv_pragma 12
optimize_registers 12
set_operating_condition 11
compile_preserve_sync_resets 11
set_multicycle 11
dft_drc 11
check_design 11
define_name_rules 11
set_input_transition 11
all_fanin 11
set_dont_use 11
write_spice_deck 11
synopsys full_case parallel_case 11
systemc sc_uint 10
tf_setdelay 10
acs_read_hdl 10
lsi_10k 10
sdf_annotate 10
case_analysis_sequential_propagation 10
dc_shell tcl 10
wire_load 10
damem_read 10
set_propagated_clock 10
parallel_case 10
set_clock_skew 10
set_isolate_ports 10
max_capacitance 9
ambit sizeof_collection 9
set_auto_disable_drc_nets 9
dw_ecc 9
set_output_delay min 9
add_to_collection 9
dc_shell_status 9
verilogout_equation 9
delay_mode_zero 9
vital_timing 9
dc_shell interview 9
parse_proc_arguments 9
hdlin_enable_presto_for_vhdl 9
set_min_library 9
set_disable_timing 9
set_multicycle_path -setup 8
fsm_perl 8
max_fanout 8
pt_shell 8
hookup_testports 8
parse_proc_arguments tcl 8
report_power 8
define_proc_attributes 8
set_false_path -through 8
set_annotated_delay 8
set_input_delay set_output_delay 8
type manager text_file_delta failed create_version operation 8
set_fix_multiple_port_nets 8
synopsys set_dont_use 8
type manager text_file_delta failed 8
synopsys dont_touch 8
snps_clock_gate 7
nsda_module 7
sdfout_no_edge 7
get_pins 7
get_timing_path 7
failed create_version operation 7
synopsys read_lib 7
set_signal_type 7
xg_mode 7
clocked_on_also 7
dc_shell xg 7
set_disable_timing set_false_path 7
hdlin_latch_synch_set_reset 7
set_max_dynamic_power 7
primetime create_clock 7
insert_scan 7
set_clock_uncertainty 7
hdlin_use_cin 7
change_name synopsys 7
cooley verilog users parallel_case twins of synthesis 7
set_scan_segment 7
set_clock_group 7
synopsys in_place 7
dc_shell area report 7
dc_shell foreach 6
report_constraint -all_violators 6
synopsys report_power 6
synopsys set_load 6
synopsys_dc.setup 6
dc_ultra 6
set_congestion_options 6
input_delay output_delay 6
dw02_multp 6
default_max_transition 6
select_op 6
define_design_lib 6
$damem_declare 6
dont_touch_network 6
insert_dft 6
define_name_rules tcl 6
all_registers 6
dc_shell xg_mode 6
wire_load timing 6
extract_model 6
do_extract_model 6
//synopsys sync_set_reset 6
timing_report_unconstrained_paths 6
set_max_capacitance 6
compile_delete_unloaded_sequential_cells 6
systemc sc_bv 6
slew_lower_threshold_pct_rise 6
synopsys set_implementation 6
set_clock_gating_style 6
dc_transcript 6
primetime write_spice_deck 6
error: type manager text_file_delta failed 6
balance_buffer 6
set_scan_transparent 6
vhdl array of std_logic_vector 6
size_cell primetime 6
synopsys connect_net 6
hdlin_infer_mux 5
s_d_lew 5
dw_fifoctl_s2_sf 5
max_transition violation 5
set_output_delay -min 5
fanout_load 5
array of std_logic_vector 5
minimum output pin drive strength ac_shell 5
full_case parallel_case 5
translate_off synopsys 5
recovery_rising 5
compile_physical 5
novas_fli.dll 5
set_equivalence 5
set_test_methodology 5
verilog all signals in hierarchy shm_probe 5
pe_shell 5
synopsys_translate_on 5
dw_fifo_s2_sf 5
compile_map_for_area 5
propagate_constraints 5
pt_shell commands 5
synopsys all_inputs 5
.synopsys_dc.setup tcl 5
xor_reduce 5
set_scan_signal 5
shm_probe options 5
dw_16550 5
get_plus_arg 5
psyn_shell 5
report_net 5
text_file_delta: error 5
neg_tchk vcs 5
synopsys report_area 5
report_power_calculation 5
scan_enable 5
synopsys dc_script_begin 5
no_notifier 5
set_implementation 5
create_test_clock 5
design_compiler 5
compile_new_optimization 5
read_parasitics 5
synopsys create_clock 5
std_logic vs std_ulogic 5
update_timing 5
slew_lower_threshold_pct_fall 5
verilog $shm_probe hierarchy 5
compile_fix_multiple_port_nets 5
write_sdf 5
remove_unconnected_ports 5
primetime get_attribute 5
-- synopsys translate_off 5
can't find lib_pin 4
design compiler report_area 4
acc_fetch_fullname 4
select_op synopsys 4
compile_seqmap_synchronous_extraction 4
dc_shell environment variable 4
set_output_delay hold 4
primetime set_load 4
dw_16550 area 4
clean_buffer_tree 4
infer_mux 4
compile_sequential_area_recovery 4
set_ungroup 4
delay_mode_zero ncverilog 4
synopsys get_attribute 4
primetime create_generated_clock 4
timing_sense verify 4
report_qor 4
pt_shell unconstrained path 4
dc_shell tcl script 4
synopsys pe_shell 4
delay_mode zero 4
astro set_case_analysis 4
design compiler change_names 4
clock set_dont_touch synopsys 4
dc_shell find object 4
set_input_delay dc 4
create_clock period 1e design compiler 4
set_false_path synopsys 4
rise_resistance 4
tcl add_to_collection 4
set_false_path through 4
full_clock_expanded 4
dc_shell_status tcl 4
set_input_delay primetime 4
compile_preserve_subdesign_interfaces 4
math_real.vhdl 4
psyn_gui 4
intrinsic_rise 4
create_clock -add 4
full_case 4
get_unix_variable 4
tf_dostop 4
damem_write 4
set_flatten 4
tk in psyn_gui 4
on_chip_variation 4
//synopsys infer_mux 4
boba_fett 4
critical_range 4
set_multicycle_path examples 4
hdlin_translate_off_skip_text 4
auto_wire_load_selection 4
gtech select_op 4
combinational logic timing constraint input_delay 4
dc_shell 4
dc_shell dump log 4
pulling_resistance_unit 4
ncelab delay_mode 4
set_case_analysis synopsys 4
dc_shell tcl mode 4
dw02_mult 4
dc_shell tutorial 4
report_annotated_parasitics 4
report_delay_calculation 4
set_test_isolate 4
set_test_assume 4
synopsys change_name 4
to_stdlogicvector can not have such operands in this context 4
dc_shell tcl example 4
set_compile_partitions 4
default_input_pin_cap 4
dc report_qor 4
dw_16550 designware hdl 4
create_clock waveform 4
vhdl synopsys translate_off 4
set_false_path asynchronous 4
set_scan_element 4
dc_shell insert buffer 4
set_clock_gating_style scan 4
$sdf_annotate 4
false_path 4
$damem_read 4
primary unit std_logic_arith not found in library ieee 4
fix max_capacitance 4
vhdl translate_off 4
synopsys set_min_delay 4
check_timing 4
set_scan_signal hookup 4
clearcase text_file_delta failed create_version 4
set_unconnected 4
ideal_network 4
read_ddc 4
characterize_context 4
run_proj 4
simplify_constants 4
get_attribute primetime 4
convert std_logic_vector to bit_vector 4
default_max_fanout 4
acc_fetch_defname 4
acc_set_value 4
set_multicycle_path example 4
update_lib 4
set_false_path -through 4
verilog delay_mode_zero 4
dc_perl 4
set_input_delay syntax 4
ncverilog delay_mode_unit 4
dc_shell sram .lib tutorial 4
set_input_delay -min 4
write_script 4
dw01_add 4
dw_foundation 4
synopsys update_lib 4
vhdl array std_logic_vector 4
congested psyn_shell 4
synopsys to_stdlogicvector 4
connection_class 4
synopsys logic_0 4
set_false_path help 4
verilog pli tf_putp 4
set_port_fanout_number 4
set_input_delay min 4
define_name_rules restricted 4
report_reference 4
dc_shell work directory 4
dc_shell variables 4
set_false_path help 4
where to use .lib in dc_shell 4
synopsys resource map_to_module 4
dc_shell optimization 4
formality name match dc_shell 4
constant a : std_logic_vector(4 downto 0) := '0' & x e 3
design compiler set_false_path 3
create library lib synopsys write_lib 3
tcad_grd_file 3
download lsi_10k.db library 3
replace_synthetic 3
related_pin output 3
test_default_bidir_delay 3
nc verilog no_notifier 3
use error_info for more info. (cmd-013) 3
set_annotated_check 3
dc_shell memory usage 3
dc_shell scripts scan insertion 3
synopsys group hdl_block 3
all_registers in dc_shell 3
condition for max_transition in synopsys lib 3
set_scan_chain 3
all_connected 3
all_registers -clock_pins 3
design compiler ideal_net 3
dc_shell libext 3
removing dont_touch from design 3
synopsys driver_cell 3
synopsys get_license 3
vhdl case dont_care 3
synopsys library timing_range 3
verilog disable_warning 3
synopsys critical_range 3
synlib_wait_for_design_license 3
dc_shell check license 3
type manager text_file_delta failed 3
bit_width vhdl 3
synopsys_pt 3
// synopsys translate_off 3
async_set_reset_local 3
dc_script_begin 3
multi_cycle_path 3
multisource_int_delays 3
dc_shell remove dw01 3
esnug set_dont_touch_network set_ideal_net 3
get_clocks 3
wire_load_from_area 3
compile_use_low_timing_effort 3
remove_attribute dc_shell 3
dc_shell conversion pks 3
partition_dp 3
dc_shell find cell 3
report_timing synopsys 3
dc_shell read 3
edifout_target_system cadence 3
delay_mode 3
group_path 3
create_clock gating 3
report_delay_calculation primetime 3
optimize set_dont_touch_network 3
how to use sc_bv systemc 3
failed create_version 3
set_false_path clock 3
disable_timing 3
test_cell() liberty format 3
set_load -su 3
report_timing -group 3
$shm_probe options 3
design_analyzer error id 3
dc_shell-t command 3
convert dc_shell to tcl 3
acc_handle_object 3
design compiler xg_mode 3
acs_num_parallel_jobs 3
dc_shell sed 3
disable_warnings verilog 3
$disable_warnings 3
set_max_leakage_power 3
assigning hex values to std_logic_vector 3
create_generated_clock primetime 3
set_scan_state test_ready 3
set_load design compiler 3
set_case_analysis astro 3
dc_shell-xg 3
do_build_generic 3
group_path synopsys 3
synopsys set_max_delay 3
verilog disable_warnings 3
conv_integer modelsim 3
primetime set_ideal_network 3
cell_of 3
synopsys dont_touch_network reset 3
to_stdlogicvector vhdl 93 3
max_transition violated 3
resize numeric_std 3
timing loop problem dc_shell 3
signal type for multiplexed_flip_flop 3
link_library 3
asynchronous create_clock 3
create_generated_clock -edges 3
set_multicycle_path primetime 3
create_operating_conditions 3
change_names -rules verilog 3
set_driving_cell clock port 3
xor non_unate 3
file check inside dc_shell 3
synopsys all_registers 3
all_clocks 3
std_logic_arith vs numeric_std 3
current_instance synopsys 3
Total 11,370
internal DeepChip search keywords
generated_clock 26
report_area 22
set_false_path 20
create_generated_clock 20
set_multicycle_path 19
Primetime write_sdf 13
sync_set_reset 12
set_clock_latency 12
dc_shell 11
set_max_transition 11
dc_shell clock 11
wire_load 10
run_celtic 10
synopsys clocks create_clock 10
set_ideal_net 9
set_load sdf 9
scan_compression 9
Chip AND set_input_delay 8
dc_shell interconnect area 8
set_clock_uncertainty 8
design_vision dc_shell gui 7
full_case 7
set_input_delay 7
multiple clocks set_input_delay 7
timing disappears after insert_scan 7
write_sdf script 7
on_chip_variation 7
reoptimize_design runtime 7
generated_clocks 6
write_sdf 6
dc_shell makefile 6
write_sdf script clock 6
set_output_delay 6
multiple clock register dc_shell 6
set_timing_derate 6
set_ideal_network 6
clock latency set_input_delay encounter 6
generated_clock liberty 5
dont_touch 5
fix_multiple_port_nets 5
compile_ultra 5
optimize_registers 5
check_timing 5
set_output_delay more one clock 5
tsmc13_wl10 5
timing_dynamic_loop_breaking 5
set_load sdf different 5
dc_shell writing svf 4
wire_load_selection tsmc 4
PAD pulse_r 4
bc7_7 layout 4
set_max_delay 4
insert_scan 4
report_timing 4
verify_false 4
input_delay 4
allocate_budget 4
set_max_area 4
set_false_path -through 4
Incremental_mapping 4
max_transition 4
set_resistance 4
set_fix_multiple_port_nets 4
sdf_annotate 4
reoptimize_design flow 4
timing_report_unconstrained_paths 4
fanout_load 4
set_fanout_load set_max_fanout 4
inout tran dc_shell 4
check_timing relate 4
sync_async 4
create_generated_clock set_clock_latency 4
wait for dc_shell license 4
tsmc13_wl30 4
write_spice_deck 4
loop_breaking primetime 4
remove_unconnected_ports 3
read_def 3
create_generated_clock falling edge 3
source_libs 3
reoptimize_design 3
bc_7 boundary scan layout 3
EIDF _0_0_ 3
report_timing -justify 3
constrain designs multiple clocks set_input_delay 3
set_output_dealy on more than one clock 3
compile_seqmap_synchronous_extraction 3
nc_sim exit codes 3
synopsys generate_clock 3
sta set_case_analysis 3
synopsys clocks create_cloc 3
dc_fpga 3
timing_self_loops_no_skew 3
test_ready Scan routing is not comp 3
balance_buffer 3
clock_fall 3
constraints disappear after insert_scan 3
related_pin 3
set_disable_timing AND set_false_pa 3
_reconvergence_pessimism 3
_sel 3
set_cost_priority 3
set_drive 3
parallel_case 3
set_output_delay imaginary clock 3
mux_op 3
set_fanout 3
test_mode 3
synopsys_unconnected 3
wire_load_model 3
DFT_Compiler 2
DW_16550 UART 2
adv_superlog 2
nc_sim status codes 2
crtical_range 2
set_critical_range 2
async_set_reset 2
clock mux case_analysis 2
set_clock_transition 2
loop_breaking 2
xg_mode vcc 2
remove_port 2
set_output_delay multiple clocks 2
vcs uniform math_real 2
set_propagated_clock 2
wire_load dc_shell interconnect are 2
translate_off 2
disable_timing false_path differenc 2
liberty define_group 2
disable_timing false_path 2
astro sdram set_output_delay 2
change prompt dc_shell tcl 2
D_NET 2
celtic run_celtic 2
delay_mode_distributed 2
hdlin_keep_signal_name 2
unconstrained endpoints insert_scan 2
xg_mode power 2
pragma sync_async 2
sdc Astro set_false 2
check_bus_indexing 2
_inst vhdl 2
group_path 2
pt_allocate_budget 2
_reconvergence_pe 2
SELECT_OP 2
write_sdf 2
report_cell types 2
stdio_h 2
dc_shell-t include directive 2
Total 1,042
external Total 11,370 + internal Total 1,042 = score 12,412
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