( ESNUG 412 Item 9 ) -------------------------------------------- [05/22/03]
Subject: ( SNUG 03 #6 ) "Aart's Favorite System Tool Of The Year 2004"
> VOTED OFF THE ISLAND: One of the side effects of Aart now supporting
> System Verilog is that it's an indirect VHDL smackdown. It's a zero sum
> game. System Verilog can't own the future without killing off the VHDL
> past and some of the more religious VHDL users reacted in ESNUG 411 #6.
>
> - from http://www.deepchip.com/items/snug03-06.html
From: Pasi Tukiainen <pasi.j.tukiainen=person company=nokia sought dawn>
Hi John.
Still about Aart's keynote speech. VHDL is dead? Huh? Or the SNPS support
for VHDL is dead? Well SNPS has never supported VHDL. SNPS supports only
a subset of IEEE-1076. And somehow this subset quite closely resembles
Verilog. So why bother kicking VHDL. For an elaboration tool it should be
a quite trivial task to translate a Verilog subset of VHDL to Verilog. And
after that we engineers just don't care, a netlist is a netlist. We just
pick the one that is faster to simulate and causes you less problems with
backend tools.
However in the RTL world VHDL has two very powerful features: configurations
and entity-architecture separation. These together are very useful e.g. for
someone who wants to be technology/foundry independent. Or for someone who
has many implementations of a certain function, others optimized for
performance, others for low-power, others for area, others for RTL
simulation. Or for someone who is required to produce many ASICs with
small variations quickly...
OK, I know (or hope at least) that it was all about the system tools. It
seems however that Aart has a new system tool for every SNUG meeting.
Therefore we could arrange a bet for the "Aart's favorite system tool of
the year 2004". But then again betting is illegal here in Finland.
- Pasi Tukiainen
Nokia Mobile Phones Tampere, Finland
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