( SNUG 03 Item 6 ) ----------------------------------------------- [05/14/03]
Subject: Synopsys VCS, Cadence NC-Sim, Mentor Modelsim, Scirocco
VOTED OFF THE ISLAND: One of the side effects of Aart publically supporting
System Verilog is that it's an indirect VHDL smackdown. It's a zero sum
game. System Verilog can't own the future without killing off the VHDL past
and some of the more religious VHDL users reacted in ESNUG 411 #6. Other
than that, the big change in simulators is that they've gone mostly mixed:
Dataquest FY 2001 Simulator Markets (in $ Millions)
Verilog Total ############# $52.4
Synopsys ####### $28.0 (53.4%)
Cadence #### $16.7 (31.9%)
Fintronics # $4.2 (8.0%)
others . $2.1 (6.7%)
Verilog/VHDL
Mixed Sim Total ################################### $141.4
ModelTech ################# $66.6 (47%)
Cadence ################## $73.5 (52%)
others . $1.4 (1%)
VHDL Total ## $10.0
Aldec ## $7.8 (77.7%)
Synopsys . $2.0 (20.1%)
others . $0.2 (2.2%)
In technical terms, Cadence NC-Sim/NC-Verilog are roughly equal to Synopsys
VCS (or that's what the users are saying.) No interest in Scirocco, though.
"We use VCS, used to use NC, switched to VCS to sweeten a Synopsys
package deal. We switched at a time when both tools were having major
releases so we can't really compare. So far we really like Virsim and
didn't buy Debussy because although Virsim is no where near as powerful
as Debussy it was close enough to not allow us to skip the extra cost."
- Martin Gravenstein of Time Domain Corp.
"VCS is 10% faster then NC-Verilog. (I forget the exact release numbers
we tested, but it was pretty up-to-date versions.) However, we're more
comfortable with NC-Sim for mixed (VHDL/Verilog) simulations."
- David Lau of PMC-Sierra
"VCS for design, NC/Verilog-XL for sign-off. VCS is slightly faster
than NC for our benchmark case (400 K gates, post layout simulation)."
- Tie Li of Applause Technolgy
"Synopsys Scirocco VHDL simulator doesn't interest us and we use VHDL."
- [ An Anon Engineer ]
"I've used all three. At this company we use Model Tech. It is nice
from the user interface and debugging."
- Dave La Rosa of Microchip Technology
"We're benchmarking VCS and Modelsim. VCS Verilog is much faster. But
Modelsim has a more robust/proven mixed-language environment."
- Wilson Chan of Qualcomm
"I prefer Modelsim, but we're now using VCS. We've been quite happy
with VCS. It doesn't have the same rich debug environment as Modelsim,
but other than that its ok. I like the built-in code coverage. I
can't comment on NC-SIM."
- [ An Anon Engineer ]
"We recently did a comparison of VCS and ModelSim SE. We were attracted
to the substantial cost savings the ModelSim offers. We've tested them
both with our latest Verilog design. We've compared VCS version 6.1
against ModelSim SE 5.7a (their latest I believe) on a Linux PC box
(AMD 1.67 GHz, 2GB phys mem, Red Hat 6.2) and found:
(a) design compile time and memory usage:
The ModelSim SE compiles much faster than VCS. But it turns out that
much of the "real" compilation occurs when you launch the simulator
(vsim). The compiler (vlog) appears to be a light source code
elaborator. However, the SE took between x2-x3 the memory of VCS
during compilation.
(b) simulation runtime and memory usage:
The simulation runtime between the SE and VCS varied based on the size
of the test, but on the average SE took x5 longer to run, and took x3
the memory of VCS.
(c) PLI (1.0) implentation differences:
We tried to "convert" some of our transactor code to run on SE. Some
PLI (1.0) calls which worked on VCS did not work on SE. The Mentor FAE
was very helpful in tracking this, and pointed out that the VCS
implemtation of the PLI call was not OVI compliant, and thus should not
have worked in the first place."
- Joon Lee of SafeNet, Inc.
"NC is much much faster than Modelsim for mixed language."
- Ross Swanson of Flextronics
"We use VCS and I'm pretty happy with it. I haven't personally
benchmarked it against Cadence, although it was done here and we're
still using VCS. We don't use VHDL."
- [ An Anon Engineer ]
"We currently use VCS. We've had Cadence try converting our design to
NC-Verilog, but there has been no progress there - core dumps, etc.
So, I can't really compare them yet, other than that VCS works, and
the NC-Verilog doesn't. We're transitioning away from VHDL, so
Modelsim, NC-SIM, and Scirocco are not of interest."
- [ An Anon Engineer ]
"We use ModelSim only! Cadence NC-Sim benchmarked very bad last year
on a company-internal benchmark. Although Cadence offered a very cheap
licensing schema to introduce NC-Sim we stuck with ModelSim. ModelTech
is great!"
- Markus Schutti of Infineon
"Used NC-Verilog long ago. Used Modelsim last year. Use VCS now. I've
taped-out small, medium, and large chips with them. I don't really see
any problem with any of them. Similar capabilities. Similar speed
(they catch up with each other quickly), similar options, similar
problems.
No info on Scirocco."
- Santiago Fernandez-Gomez of Pixim, Inc.
"I prefer to run ANY simulator EXCEPT NC-SIM. My personal benchmarks
put NC-SIM as the slowest of the three simulators, especially when you
have to run mixed language simulations, as I always do. Their
documentation is pathetic, and the Cadence support people are clueless.
My personal preference remains with Modelsim. It is up to 7 times
faster than NC-SIM, and doesn't have the dual-program encumbrances of
VCS-MX. Unfortunately for me, and due strictly to political reasons,
Modelsim is no longer the preferred simulator at my company. I've also
noticed significant price increases in Modelsim over the last couple
years, which was Modelsim greatest advantage. Shame on you Mentor!"
- [ An Anon Engineer ]
"We use both NC-Verilog and VCS extensively. VCS has far better
support. VCS has the edge in speed. But VCS was/is more expensive.
ModelTech is too low end, and too slow on Verilog. No VHDL here. Some
debate on Verilog-2000 support between vendors, and where Verilog is
heading. PLI 2.0 is still not quite fully supported on VCS yet that
I am aware of. NC-Verilog has had PLI 2.0 support for years now. It's
cagey, but works for some subtle TB initilization stuff."
- [ An Anon Engineer ]
"NC-Verilog -> Fastest, excellent debugging environment in 5.0, Novas
watch out! If you do mixed-signal and mixed-language
then it's even better.
The next step with Celestry UltraSim -> The best complete tool set for
Mixed Signal designs.
VCS -> Slower than NC, 10-20% slower. Strange GUI, and harder to learn
than NC-Sim Scirroco, VCS and NanoSim will have a harder time to
get users in mixed-signal. Make it easier/more user friendly.
ModelSim -> Fastest setup for tiny designs! Totally useless for big
designs, slow and painful. It's about 6 times slower than NC-Sim."
- Bengt-Erik Embretsen of Zarlink Semiconductor
"I prefer VCS although we have NC-Verilog currently. VCS error messages
are much clearer. A colleague had benchmarked the two a few years ago
while at another company and he indicated VCS was faster, although that
may no longer be true."
- [ An Anon Engineer ]
"We've been happy with VCS; we tried NC a few years ago, but were not
impressed. Once we committed to compiled simulation, we have been
satisfied with VCS. Never used ModelSim. We tried cycle-based, but
there were various issues, and we never followed through. Not sure
if that is still the case."
- Curtis Jones of Hewlett-Packard
"Here's a thought: use Globus gridware and a bunch of Win2K machines
running Modeltech. ("Redundant Array of Inexpensive Simulators" - you
heard it here first, folks). If Modeltech/PC is (say) 1/3 the price
of VCS, but 1/2 the speed, it's a deal. Hardware's free... Actually,
before you publish this, talk to me: I'm not sure I want modeltech to
realize they've got an advantage, as they'll raise their prices on me.
You can publish _after_ I purchase 20-odd Win2K licenses at a serious
bulk discount (and MTI gives me funny looks, but goes off happily to
the bank)."
- [ An Anon Engineer ]
"We're still a VCS house."
- Kris Monsen of Mobilygen
"Our division, which is in Europe, is a Modelsim shop. Most of our
designs have VHDL in there somewhere. Starting to use VCS for those
rare designs with no VHDL (for performance and OVA)."
- Brian Schaufenbuel of LSI Logic
"I prefer VCS. Ease of compiling in additional binaries for different
tools (one step by putting in extra command line options).
I haven't used ModelSim on any chips, but I do use it while teaching
Verilog and Verilog Synthesis classes quite often and I do like the
tool though it does have similar drawbacks as NC-Verilog in doing
compiles (more steps).
I don't use VHDL."
- [ An Anon Engineer ]
"We simply don't use Synopsys simulator products. We use either NC or
ModelSim, and our customers use them too. If a customer said that we
had to demonstrate a design simulating in VCS or Scirocco, then we
would have to use it. As they don't, we don't."
- [ An Anon Engineer ]
"No interest in VHDL simulators. Haven't done a benchmark. We have
32 Cadence NC-Sim licenses and have no interest in looking at another
option. EDA budget money is tight and we see no need to revisit
simulators."
- Tomoo Taguchi of Hewlett-Packard
"I pick VCS because VCS 7.0 compiles faster and the database smaller.
VCS also supports much features for verification. I believe that the
simulator does better in verification will win. Modelsim is too slow.
It is only good for Verilog/VDHL mixed simulation. We never consider
VHDL simulator because VHDL design flow usually takes 30% to 50% longer
time than Verilog design flow."
- [ An Anon Engineer ]
"VCS and NC-Verilog are like Coke and Pepsi. I don't use the others."
- Dave Chapman of Goldmountain Consulting
"We use Cadence NC-Sim dual-language because it's cheaper. We've never
really tried VCS. I've used ModelSim in the distant past but I don't
know how it compares now. We need VHDL mainly but have some Verilog IP
in the design."
- Lance Flake of Maxtor
"Historically we used VCS - very stable, predictable results (unless you
designed wrong with the inappropriate = vs. <= constructs - and even
then VCS was able to point our some of the problems.
Agere as a company decided to move to Cadence NC-Verilog, asked our
opinion, and went ahead and moved anyway. So we have a small pool
(45 VCS licenses) for regression simulations on the past device, and
all future work is with NC-Verilog.
We benchmarked the two before they switched us. Now my experience of
the 18 years I have been in this business is that whichever tool you
are using will be leapfrogged by the 'other' tool within 6 months by
some 20%. But if you stick with your current tool, avoid the
transition problems, possibly guide the tool developer in the direction
you want, bide your time, and 6 months later 'your' tool will leapfrop
the 'other' by 20% and you will be ahead in speed. And you're not
having to spend the effort in changing.
Our benchmark showed NC-Verilog ahead by (you guessed it) 15-20%. So
the company hung that as a carrot and said, 'see it is a better tool,
lets all jump on it'. In the benchmark it appeared that there was
'no effort' to switch, and with the 20% improvement, we followed
(somewhat reluctantly). When reality hit the fan, we found that there
were some gotcha's in NC-Verilog (cannot set a default A=0 at the start
of a block of logic, then re-set it to the chosen result!!!), plus
there was not waveform dumping turned on in the NC-Verilog test we ran
for the benchmark. Guess how much waveform dumping slows things down
in the new NC-Verilog? About 20%
We used ModelSim for a while, but when we could afford VCS we switched.
We find ModelSim for Verilog about 3x slower. Benchmarked Cadence
NC-SIM a long time ago, was not up to speed, but what stage are they
at in their leapfrog? Also, why go with a Cadence tool when nothing
else is Cadence in our flow?"
- Bob Lawrence of Agere Systems
"We use Modelsim on the PC and on the SUN. We've tried using NC-Sim on
the SUN, but had troubles doing simple things like timing-annotated
sims, and all the local Cadence support staff could not help us. Their
support is so poor we gave up on the effort. Modelsim on the other
hand (Mentor) has excellent support. I found a bug in a simple
utility. They fixed it in the code and sent me a new version in a few
hours. Unbelievable."
- David Frazer of Match Lab, Inc.
|
|
