( DAC'20 Item 05b ) ----------------------------------------------- [10/21/21]
Subject: CDNS Protium "dynamic duo" hooks into Palladium is Best of 2020 #5b
HOW PROTIUM CHEATS: Take your RTL straight into Protium, first initial
ramp is 4-6 weeks. But port a Palladium design into a Protium, your
initial ramp is only 24 hours. This is how FPGA-based Protium cheats!
Cadence Protium took 1 to 2 days to recompile -- while Synopsys HAPS
took 4 to 6 days to recompile.
That's why Protium's crazy fast incremental compiles yielding 8.3 Mhz
simulation speeds won the #1 Best of EDA in 2019 award from the
end users this year.
- Protium's crazy fast "Palladium-compiles" #1a for Best of 2019
BATMAN AND ROBIN: Palladium users prefer Protiums for accelerated SW runs
because they can use Palladium's design database inside the Protium boxes.
That is, they like the FPGA-based faster runtime Protium paired with the
custom uP-based faster compile/debug time Palladium *because* they play off
of each other's strengths...
... sort of like how Batman plays off Robin as the Dynamic Duo.
"Protium's compilation from the Palladium database takes care of
everything automatically without requiring manual intervention.
i.e., I don't have to tweak the ASIC design or iterate through PnR."
"Whatever database we've compiled in Palladium, we can just map it to
the same database in Protium, run Xilinx Vivado FPGA P&R, as part of
our standard Protium flow, and start our validation."
"We bought Protium because we wanted to efficiently offload Palladium,
especially for our early firmware development. The fact that Protium
and Palladium shared the same ecosystem and frontend flow made their
adoption fairly natural for us to do."
"Protium for the deep HW bug hunts. Palladium for early quick debug."
Users also like the 2-way debug between the two machines.
"Protium and Palladium also have a two-way debug compatibility."
"Protiums have the speed. Palladiums have the visiblity. Our debug
is most intense when we're jumping back and forth from Protiums and
Palladiums on an almost weekly basis."
"We even use identical SpeedBridges and IO cards for both systems."
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PLUS EASY SCALING: With the compile problem solved, the natural next
question to ask is: "well, how big of a design can I now run in a Protium?"
And the users report:
"Protium X1 is a blade-based prototyping platform, so it scales easily.
You just rack more blades. Protium's minimum granularity is
6 FPGAs/blade; within a single PRx1 rack, we can have up to 8 blades
(equal 48 FPGAs), so close to ~1 billion."
"... keeping to under 75% utilization, in our experience, Protium X1
has close to a billion-gate capacity. 6 x 8 x 25M x 75% = 900M
"Protium's capacity expandability is good; we map our engineers to
Protium slots and have them all run in parallel and fully remotely."
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SNPS BOUGHT DINI: The surprise news on early 2020 was that the notoriously
and outspokenly cantankerous Mike Dini got acquired (it must have been for
significant money!) into Manoj Gandhi's SNPS verification army.
"Dini customers aren't your typical HAPS users. They're bitcoin
miners and Wall St. blokes doing low latency stock trades.
Smart, but a very niche adjacency for Manoj grow into."
Also, I got the usual Zebu user comments; plus the usual macho HAPS user
comments; plus one user cite of the new HAPS-100.
"Any chip designer who isn't using HAPS isn't a real chip designer."
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QUESTION ASKED:
Q: "What were the 3 or 4 most INTERESTING specific EDA tools
you've seen in 2020? WHY did they interest you?"
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Single compile for Palladium + Protium is still our #1 this year, too.
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Since 2018, we've been using Cadence Protium S1 as our preferred, go-to
FPGA-based prototyping system -- mostly for firmware and software
development.
Prior to Protium, we had a our own in-house FPGA prototyping system
that we designed ourselves. We switched to Protium S1 because:
- It was not possible to fit our entire design in our in-house
system and was just not possible to get timing closure with
without trimming down the logic. The S1 can fit our entire
design and also get timing closure automatically.
- We like Protium's compile/database compatibility with Palladium;
it makes it very easy to start using Protium.
Whatever database we've compiled in Palladium, we can just map it to the
same database in Protium, run Xilinx Vivado FPGA P&R, as part of our
standard Protium flow, and start our validation.
The process is extremely smooth, we even use identical SpeedBridges and
IO cards for both systems.
Protium and Palladium also has a two-way debug compatibility.
We were already using Palladium, and the advantage to using Protium was
so obvious we didn't do an eval of other prototyping systems.
How we use Protium with Palladium:
1. Our ASIC team deploys Palladium more often, e.g., for
co-verification.
Palladium has a full vision waveform debug advantage over
Protium, which make it better suited for ASIC engineering
debug. Early ASIC bring-up is run mostly on Palladium and
simulation as it requires more debugging at that stage.
2. Our firmware/software engineers run Protium more often,
generally after the design has matured a bit.
We typically run Protium for simulation acceleration of our
subsystems and for in-circuit prototyping of our entire design
(talking to external devices).
Protium has a 4X-5X speed advantage over Palladium. If we
can get 1.75 MHz with Palladium for our design, we will get
~ 8 MHz speed from Protium.
Both verification flows are always active, and our teams use them in
parallel -- it's not a single direction flow. For example:
- Protium is fine for the first step of debug, but we must
pre-select what we want to debug, e.g., the 1000 signals we
want to look at. If our choice is not right, we rerun it for
different signals.
- Palladium gives us full visibility, so it's better for deeper
analysis. If our firmware/software engineers find a
complicated bug, they usually take the design back to Palladium.
Conclusion --
Protium adds value to teams using Palladium; it's a great counterpart.
Additionally, Protium's capacity expandability is good; we map our
engineers to slots of Protium and have them all run in parallel and
fully remotely.
---- ---- ---- ---- ---- ---- ----
4 weeks to compile in Palladium. 2 days mapping into a Protium.
Or 4 to 5 months into a Zebu.
Easy choice.
---- ---- ---- ---- ---- ---- ----
Cadence Protium X1
We currently use both the Protium S1 and Protium X1 for prototyping.
We bought Protium because we wanted to efficiently offload Palladium,
especially for our early firmware development. The fact that Protium
and Palladium shared the same eco system and frontend flow (and only
needed one common compile) made the adoption fairly natural.
Cadence understood Protium needed good debugging capabilities had to
happen; so they added new hardware and data capture cards to get it
close to what Palladium offers.
However, Palladium debug and wave capture is so easy (and powerful)
guys still prefer it for debug. (Palladium gives us more probes with
full vision. So, if we find a design issue when running Protium,
we go back to Palladium to debug it.)
Protium X1 is a blade-based prototyping platform, so it scales easily.
You just rack more blades.
- Protium's minimum granularity is 6 FPGAs/blade; within a single
PRx1 rack, we can have up to 8 blades (equal 48 FPGAs), so close
to ~1 billion.
- The Xilinx UltraScale docs say 25 M gates-per-FPGA, though
that number is theoretical.
- We find as long as we keep Protium X1 under 75% utilization,
it has always worked well for us with no problems.
- So in our experience, Protium X1 has close to a billion-gate
capacity. 6 x 8 x 25M x 75% = 900M
Set up time For Protium S1 & X1
The total setup time is not totally controlled by Cadence, as after
Protium compiles, we must run Xilinx PnR for our 70% utilized FPGA.
Design size Protium compile Xilinx PnR time Total time
----------- --------------- ---------------- -----------
20M gates 1-2 hrs + 12-15 hrs == 13-17 hours
450M gates 13 hrs + 12-15 hrs == 25-28 hours
For both Protium S1 & X1, with their super tight hooks into Palladium
makes them great for offloading our longer Palladium runs.
Protium's compile from the Palladium database takes care of everything
automatically. It requires NO manual intervention. i.e., We don't
have to tweak the ASIC design or iterate through PnR. It saves us a
ton of time.
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Protium runs Palladium compiles is nice, but you still have to do that
Xilinx Vivado FPGA PnR. It's not 100% seamless, but as close as you
can get with two fundamentally different gate models to map to.
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Warning: do NOT buy any Protium without having access to a Palladium.
All the Protium compile savings comes from your Palladium compile.
---- ---- ---- ---- ---- ---- ----
Heads up -- Protium runs mean you must have Palladium access or you're
scrwed. (Not a problem for us because we have a room full of Palladium
boxes. But for a smaller company this might be a problem.)
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Protium ramp up is lighting fast with our Palladiums.
It does it in ~24 hours or so.
Can't do that with any Zebu box, I tell you!
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We swapped out our Zebu's for Protiums because of its Palladium compile.
---- ---- ---- ---- ---- ---- ----
That unified HW compile for CDNS boxes was one smart move.
Saves us endless duplicate man-hours.
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Protium with Palladium
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Doing one compile for Palladiums and Protiums was a brilliant move
on Anirudh's part. I'm sure it's a cash cow for him.
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Protiums have the speed. Palladiums have the visiblity. Our
debugging is most intense when we're jumping back and forth
from Protiums and Palladiums on an almost weekly basis.
---- ---- ---- ---- ---- ---- ----
Protium S1 cause it sims 100 M gates-per-box at 7 Mhz.
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Protium X1 / Palladium Z1
---- ---- ---- ---- ---- ---- ----
If we can compile it in a Palladium, it'll port in a Protium.
That's cruicial for us.
---- ---- ---- ---- ---- ---- ----
Protium for the deep HW bug hunts.
Palladium for early quick debug.
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Protium utilization at or below 60%, everyone is happy.
Protium utilization at or above 80%, everyone is pissed.
The grey zone is 61% to 79%
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Mgmt wants Protium speed/pricing with Palladium compiles/visibility.
---- ---- ---- ---- ---- ---- ----
Protium along with Palladium.
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Aart should negotiate a deal with Anirudh to make his Zebu compiles
compatible with Palladium compiles.
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Protium-S1
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USERS ON ZEBU/HAPS/DINI HW BOXES
Zebu Server 4's.
We have enough to fill a full-sized university cafeteria with them.
---- ---- ---- ---- ---- ---- ----
We've used Zebus since forever.
We're a Zebu house.
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Our SW guys swear by our Zebu's.
---- ---- ---- ---- ---- ---- ----
Comparing Zebu vs. Protium right now.
I'll tell you how it comes out.
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We get Zebu4s at significantly reduced costs compared to Protiums.
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Any chip designer who isn't using HAPS isn't a real chip designer.
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Protium might be easier to set up, but with the right compile/PnR
we can get our HAPS-80 machines to run 4 Mhz faster.
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For our IP designs, the HAPS-80 leaves everything else in the dust.
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Our HW guys bitch and moan about how much work our HAPS boxes are.
Our SW guys tell them to shut up and to keep our HAPS boxes up.
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Takes 100 years to compile into, but we're getting 20+ Mhz speeds
with our HAPS-100 hardware. It's well worth it.
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You should check out the new HAPS-100's, John.
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PrimeTime, VCS, and Zebu 4
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We still use Dini boxes here.
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I expect Mike Dini to last 1 year at most inside Synopsys.
He's far too truthful to last inside such a political hierarchy.
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Word is Dini has a 12 month earn-out with SNPS.
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Dini customers aren't your typical HAPS users. They're bitcoin
miners and Wall St. blokes doing low latency stock trades.
Smart, but a very niche adjacency for Manoj grow into.
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How much did Dini get for selling out to Synopsys?
Do you know?
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Related Articles
CDNS Palladium Z1 speed, uptime, & cloud access is Best of 2020 #5a
CDNS Protium "dynamic duo" hooks into Palladium is Best of 2020 #5b
... and Big 3 vendors launched new HW in 2021 and users want scoops!
Sneak peeks at new Palladium X2 and new Protium X2 is Best 2020 #5c
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