Subject: The DeepChip Top 15 User-Written EDA Technical Letters of 2010

TECH MEAT: The top technically meaty EDA tool user stories of 2010 were the
ones that hit close to home; TSMC 40 nm yield, questionable PrimeTime 2X
speed-up claims, and a first look at a new verification start-up (NextOp).

             The Top 15 EDA Technical Stories of 2010
             ----------------------------------------

    1.) Can we trust that TSMC's 40 nm yield issues are now truly fixed?
              http://www.deepchip.com/items/0484-05.html

    2.) Rivals laugh at Synopsys annual PrimeTime 2X speed-up claims
              http://www.deepchip.com/wiretap/100114.html

    3.) A first look at stealth start-up NextOp's assertion synthesis
              http://www.deepchip.com/items/0484-01.html

    4.) "How many companies are actually using High Level Synthesis?"
              http://www.deepchip.com/items/0486-07.html

    5.) Aart's personal nightmare -- a first look at Oasys RealTime
              http://www.deepchip.com/items/0484-02.html

    6.) Controversies around Mentor Calibre vs. Magma Quartz benchmarks
              http://www.deepchip.com/items/0484-07.html
              http://www.deepchip.com/items/0485-06.html
              http://www.deepchip.com/items/0486-08.html

    7.) Jim Hogan ranks the commercial variation-aware full custom tools
              http://www.deepchip.com/items/0486-05.html
              http://www.deepchip.com/items/0487-07.html
              http://www.deepchip.com/items/0487-08.html

    8.) Gotchas migrating from homebrew FPGA emulation to Cadence Palladium
              http://www.deepchip.com/items/0486-01.html

    9.) A first look at Atrenta SpyGlass Physical for pre-RTL/RTL design
              http://www.deepchip.com/items/0486-04.html

   10.) A follow up user evaluation of Atoptech's Apogee floorplanner
              http://www.deepchip.com/items/0485-02.html

   11.) Mentor CatapultC user on control logic synthesis and AC Channels
              http://www.deepchip.com/items/0486-02.html

   12.) Solido caught a sneaky analog layout variation bug in our silicon
              http://www.deepchip.com/items/0487-10.html

   13.) We got 100X compression using Magma Talus Design & Mentor Tessent
              http://www.deepchip.com/items/0485-05.html

   14.) User says Solido speeds up Cadence Spectre variation design by 5X
              http://www.deepchip.com/items/0485-07.html

   15.) We transitioned from Dassault DesignSync to IC Manage in 3 days
              http://www.deepchip.com/items/0484-10.html