Subject: What Solido went through qualifying for new TSMC AMS Ref Flow

From: Amit Gupta <gupta=user domain=solidodesign got mom>

Hi John,

One of TSMC's big announcements during DAC this year was their first ever
Analog/Mixed-Signal (AMS) Reference Flow.  As far as I know they are the
first foundry to do this.

The TSMC AMS Reference Flow 1.0 was done by qualifying EDA vendor tools
using a 10,000 device, 28 nm, 1.6 GHz PLL design.

Below are the tools that qualified for the TSMC AMS flow:

   - Apache Design.  Totem for power, noise and reliability tool for
     early power/ground grid integrity check, static and dynamic IR
     drop signoff, electro-migration validation and chip power model
     generation of full custom  designs.

   - Berkeley Design.  AFS for device noise analysis simulation.

   - Cadence.  Virtuoso for design and verification of AMS IP.

   - Ciranova.  Helix for floorplanning and placement.

   - EdXact.  Jivaro netlist reduction software.

   - Magma.  Titan mixed-signal design and FineSim SPICE and FineSim Pro
     circuit simulation.

   - Mentor Graphics.  ICanalyst functional verification, Eldo simulator,
     ADiT high capacity simulator, Calibre xACT 3D parasitic extraction,
     Calibre PERC automated electrical rule checking, Calibre nmDRC/LVS.

   - Pyxis Technology.  NexusRoute-HPIC for routing power & signal nets.

   - Silicon Frontline.  F3D parasitic extraction for post-layout
     verification.

   - Solido Design.  Variation Designer for variation-aware custom IC
     design used to analyze and fix variation effects caused by PVT
     corners, local and global random variation, and proximity effects.

   - SpringSoft.  Laker custom layout.

   - Synopsys.  Custom Designer, HSPICE, CustomSim FastSPICE simulator,
     StarRC parasitic extractor and IC Validator physical verification.

TSMC put us through a rather thorough process to get qualified.  

First, TSMC did an extensive evaluation of our tool on a number of designs
themselves and looked at who our common customers are.  We then worked
extensively with a TSMC CAD engineer on a test 28 nm PLL:

  1. For PVT (process, voltage, temperature) corner design using TSMC
     process corner models.
  2. For efficient statistical design beyond traditional Monte Carlo
     analysis utilizing TSMC statistical variation models for both
     global and local random variation.
  3. To analyze and fix systematic layout effects due to well proximity
     using TSMC proximity effect models.

Both a Solido AE and a TSMC CAD engineer completed the work.  The TSMC
Reference Flow group in Taiwan worked with a Solido AE here in North
America on the reference design.  Our portion of the reference design
took about a man-week of effort to complete.

Here's TSMC's data on Solido's before/after impact on their 28 nm PLL
when it was designed to 6 sigma.  TSMC used Solido with Cadence Spectre
and Synopsys HSPICE.
                                         Before    After Solido
                                         ------    ------------
  Analyze effects of PVT variation         -        Done
  Identify PVT device sensitivities        -        Done
  Analyze effects of global and local      -        Done
     random variation
  Identify device sensitivities to         -        Done
     random variation
  Improve average current mismatch        1.67%     0.68% (59% better)
  Improve current mismatch yield          64.3%     98.5% (34% better)
  Improve chip area                       758u^2    736u^2 (3% better)
  Improve output duty cycle variation     0.61%     0.50% (18% better)
  Improve frequency variation             8.32%     5.97% (26% better)
  Verify duty cycle yield                  -        6 sigma yield
  Identify device sensitivity to well      -        Done
     proximity effects (WPE)

If you were to run Monte Carlo analysis in a circuit simulator like Spectre
or HSPICE without Solido it would take more than 10 billion samples to
verify a design to 6 sigma -- meaning that 99.9999998% of designs will work
despite variation.  This of course is an impractical number of simulations
to run.  Solido has a "Verify High Sigma" capability that biases sampling
to the tails of the distributions.  So, instead of having to do 10 billion+
samples, only 28,000 samples were required for this test PLL.

As the final part of the eval, TSMC taped out their test 28 nm PLL, fabbed
it, and confirmed in silicon the parameters that Solido had improved.

After all that, and only then, we were added to the new TSMC AMS flow.

    - Amit Gupta
      Solido Design Automation                   Saskatoon, Canada