The Wiretap Intercept No. 090806
opinions and skeptical speculations too small to fit into an Industry Gadfly column

Subject: Dave Chapman on "maybe C synthesis has finally grown up"

> I think it's important to know that this data is NOT pointing to a mass
> movement towards C for general chip design -- what its pointing to is that
> chip designers are now interested in C synthesis tools (i.e. EDA tools
> that read in C/C++/SystemC source and synthesize out Verilog/VHDL RTL.)
>
> Why?  I don't know.  Are designers now going off into the la-la land of
> "higher levels of abstraction" in C?  I don't know, but I doubt it.  All
> of these items are on the PRACTICAL aspects of synthesizing C/C++/SystemC
> into Verilog/VHDL RTL only -- not that la-la fruity virtual protyping crap
> nor vague architect's workbenches nor target compilers nor wackadoodle
> co-simulators nor mystery model BS -- they're purely the nuts-and-bolts of
> making C/C++/SystemC source code into RTL (C synthesis) AND NOTHING MORE!
>
>     - from http://www.deepchip.com/gadfly/gad071409.html


From: Dave Chapman <dave=user domain=goldmountain not balm>

Hi, John,

As an early C-for-chip-design skeptic (and a guy with many years experience
programming C), I think that I can tell you what the deal is:

  1. There's a generational change.  20 years ago, most RTL designers didn't
     know how to program.  Today, it's required for *all* EE undergraduates,
     with the result that RTL designers today are a lot more familiar (and
     comfortable) with C and C++ than before.

  2. The level of ridiculous hype for C has dropped a lot.  This means that
     it is now possible to consider using C for a chip design without
     feeling like you've joined a strange cult.

  3. C has proven, IN SOME CIRCUMSTANCES, to be a useful tool for the
     design of high-level functionality.  People are therefore using C when
     it gives them a "nuts-and-bolts" advantage over plain old Verilog.

  4. The quality of C tools have improved a lot.  One extremely important
     factor is the non-adoption of early C-to-Verilog tools was the fact
     that they produced crappy RTL.  This has (apparently) been fixed.

Maybe, just MAYBE, C synthesis has finally grown up.  This is just one guy's
view and the usual disclaimers apply.

    - Dave Chapman
      Gold Mountain Consulting                   Sebastopol, CA

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