> San Jose, CA, 18 May 2009 -- Developed by Taray, and available to Cadence
> customers through an OEM agreement, this exclusive joint solution offers
> an optimized correct-by-construction FPGA pin assignment that reduces the
> number of pin optimization iterations during PCB layout while reducing
> the number of layers required to route the FPGA on a PCB design.  Allegro
> FPGA System Planner also shortens time for companies using FPGAs on PCB
> systems to emulate their ASICs through automated FPGA pin assignment. 


From: John Isaac <john_isaac=user domain=mentor.com>

Hi John,

Saw the Cadence OEM agreement with Taray for a FPGA-PCB tool.  Wanted to
give you some comments, but it's difficult.

I wanted to to do a point by point comparison of Taray vs. Mentor, but it's
tough to understand what Taray really has for capabilities.  Everything
publically available on the web is too vague!  Apparently Taray is very
new.  We've yet to see them in any customer accounts.  As best as I can
tell they're an FPGA-PCB I/O tool.

Mentor first delivered a similar product in 1997 called "BoardLink" which
integrated FPGA design in our Expedition PCB flow.  Major enhancements were
added in 2005 and delivered as a new product called "I/O Designer".

Synplicity doesn't compete in this space because they lack PCB tools.

The only other FPGA-PCB co-design tools I know of is from Altium.  But
Altium only addresses the low-end market where the PCB designs are simple
and the challenges of implementing FPGAs are minimal.

Wish I could comment more about this Cadence-Taray deal, but there's not
much hard public information I could find about it.

    - John Isaac
      Mentor Graphics SDD                        Longmont, CO