I was getting pitched by the IC Manage people about some extremely yawnable
Design Management something and three bits of accidental data jumped out at
me.  They had done a survey of 416 engineers.  They asked and got:

    "What percentage (%) of your time do you estimate is spent on
     Design Management issues such as tracking down IC-related design
     files or a specific configuration of files?"

                 under 5% :  : ######################### 25%
                       5% :  : ############## 14%
                      10% :  : ################## 18%
                      15% :  : ############ 12%
                      20% :  : ############# 13%
                      25% :  : ##### 5%
                      30% :  : ##### 5%
                 over 35% :  : ### 3%

             average time
              spent on DM :  : ############ 12%

So on a typical 12 month chip design project, one should expect to spend
6.24 work-weeks just on keeping track of ECO's, rev control, etc.

Their second piece of data:

    "Has your organization ever missed a project deadline or delayed a
     tapeout due to Design Management issues such as version control or
     configuration management?  If yes, for how long a delay?"

             never missed :  : ################################### 47%

                 1-2 days :  : ### 3.4%
                 3-5 days :  : ###### 8.0%
                1-2 weeks :  : ###### 8.0%
                3-4 weeks :  : ####### 9.7%
               1-2 months :  : ####### 9.7%
               3-4 months :  : 0%
               5-6 months :  : 0%
                6+ months :  : ### 3.4%

             average time
        lost to DM errors :  : ################ 16 work days

So for any given project, there's a roughly 50-50 chance some sort of DM
issue will burn you and it's set you back, on average, 16 work days.

And then their third piece of data:

    "What's the top 3 main reasons your organization uses DM for?"

          Easier to track
             and fix bugs :  : ############################## 60%

           blah blah blah :  : ############################# 58%

           blah blah blah :  : ################### 39%

It's that top reason which got 60% of the audence's attention that caught
my eye -- "Easier to track and fix bugs" -- we have a special single word
in English that has the exact same meaning.  It's called "verification".

Christ!  I've seen this before!  In ESNUG 479 #4 in Mentor's C-synthesis
survey data:

     "What are the 2 biggest reasons to use High Level Synthesis?"

                Faster time to RTL :  ######################## 64%
          Faster verification time :  ################## 49%
       Fewer engineering resources :  ############ 31%
                        Fewer Bugs :  ####### 19%
      C RTL better than hand-coded :  ##### 14%
         Faster ECO implementation :  ### 8%
    Better product differentiation :  ### 7%
                             Other :  ## 4%

           - from http://www.deepchip.com/items/0479-04.html

Now focus just on all the "verification" reasons and you see:

          Faster verification time :  ################## 49%
                        Fewer Bugs :  ####### 19%
      C RTL better than hand-coded :  ##### 14%
         Faster ECO implementation :  ### 8%

Long story short, two completely different (and unrelated!) approaches to
DESIGN are moving forward because they solve VERIFICATION problems.

Who'd have thunk yawnfest DM and wave-of-the-future C-synthesis would be
making almost the exact same sales pitch?  LOL!

    - John Cooley
      DeepChip.com                               Holliston, MA