You may have missed it last week, but Richard Goering wrote an interesting
article in EEtimes.com about how System Verilog is being used for functional
test assertions, but not as an actual design language.

   "'I thought designers would pick it up first, but they're a little
     more cautious about it,' said Cliff Cummings, president of the
     training firm Sunburst Design Inc.  Verification engineers, he
     conceded, need only a simulator to use System Verilog, while
     designers require synthesis, simulation and linting tools."

What's interesting in all this is that Superlog...  er, ah..  Correction,
make that "System Verilog" started out as a Synopsys acquisition of
Simon Davidmann's Co-Design Automation company waaaaaay back in September
of 2002 -- which is almost 5 years ago.

OK, so System Verilog wasn't an IEEE standard until late 2005, but you'd
think with a 5 year head start, Synopsys would have had a boatload of users
yarping about using their System Verilog synthesis, simulation and linting
tools by now.  But they don't.  Lots of assertion testbench use (just like
Cadence and Mentor) but hardly anyone's barking about it for real life
synthesis and chip design.

According to the article the Accellera folks say that by now 136 EDA vendors
will be offering at least 350 System Verilog tools this year.

Now I'm left wondering.  For simulators, Synopsys, Cadence, and Mentor are
all in the same herd supporting SV at pretty much the same level.  But for
their flagship Design Compiler, it appears that Synopsys blew off any early
serious adoption of SV for synthesis.  Huh?  If wasn't for a head start on
the competition, why did Synopsys plunk down $36 million in cash to acquire
Co-Design in the first place?  If you're going to follow the herd anyway,
why bother paying extra for already free grazing rights?  I don't get it.