>  What are edgy questions I can ask these guys at the DVcon Troublemakers
>  panel on Thursday, Feb. 22nd?


From: Jeremy Omas <jeremy_omas=user domain=amis not calm>

Hi, John,

One thing I've been trying to get Cadence and Synopsys to respond to is
the timing difference between gate level simulations and PrimeTime.
Static timing analysis has significantly improved over the last 15 years.
The use of new calculation methods and deration capabilities, along with
statistical STA on the horizon, has provided a distinct improvement in
confidence that what is evaluated prior to tape-out is what
is produced in silicon.

However, what advances have been made in the gate level simulation?

Some may make the argument that post-layout gate simulations are not
needed since STA is so "advanced".  This topic, in and of itself, is a
long debatable issue.

However, I believe that post-layout gate level simulations are not a
thing of the past because I just don't always trust the quality of the
STA constraints.

My question Antun and Ted: What's your plan to address the stagnation in
the gate level simulators?

    - Jeremy Omas
      AMI Semiconductor                          Plano, TX