> The Synopsys Marketing press release went on to claim:
>
>     "Unlike competing tools, the TetraMAX solution does not require
>      partitioning of a large SoC to run ATPG separately on each block;
>      instead it can generate patterns for the entire design at once."
>
> So as a hands-on TetraMAX user, are you seeing Mentor FastScan choke on
> your big chips?  Is FastScan pitifully crying like a baby for partitioning
> (like how Synopsys Marketing implies in this press release) while TetraMAX
> gleefully breezes through your chip like hot knife through butter?
>
>     - from http://www.deepchip.com/wiretap/061102.html


From: Tom Jackson <tjackson=user domain=cadence not calm>
To: John Cooley <jcooley=user domain=zeroskew not calm>

Hi John,

I am writing about the controversy surrounding Synopsys TetraMAX ATPG and
the supposed performance problems of their "competition".  Like how Mentor
who has similarly commented, I am sure Synopsys Marketing is not speaking
about our Cadence Encounter Test tools in their press release.  I say this
with confidence because in the October issue of Test and Measurement World
our True-Time ATPG was featured in an article we co-authored with Qualcomm.
In the piece, we wrote about their experience testing very large and highly
complex devices using Cadence True-Time ATPG capabilities and they did not
mention any performance problems.

Additionally, there were several customers in our booth at ITC speaking in
similar fashion about testing big chips using Encounter Test and the issue of
runtime did not even come up.

At Cadence, we are always working to improve ATPG runtime but our customers
are having great success today with Encounter Test.

    - Tom Jackson
      Cadence Design Systems, Inc.               San Jose, CA

         ----    ----    ----    ----    ----    ----   ----

From: John Cooley <jcooley=user domain=zeroskew not calm>
To: Tom Jackson <tjackson=user domain=cadence not calm>

Hi, Tom,

Although I appreciate your writing in to clarify that it ain't Cadence Test
that Synopsys Marketing is trying to smear, I have to call shenanigans on
your equally lame "proof" that your True-Time ATPG is supposedly fast because
there were no speed complaints about it in a joint article Cadence co-wrote
with a customer for an official trade publication.

And then you lamely report that not one of the customers in your ITC booth
never said anything "bad" about your tool's runtime.

Oh, come on!  Who are you trying to fool?  If your users were each going
through Bug Hell itself with your True-Time ATPG, would you honestly write
and tell me this, Tom?  Would you?

Such trade pub articles and vendor booth "customer" testimonials NEVER point
out the flaws of a tool.  These are happy-happy, joy-joy puff presentations
carefully crafted to give potential customers the false illusion that your
brand of XYZ is really, honest, gosh golly the greatest XYZ in the world.

EDA marketing pitches have never been about the truth, Tom, so please don't
try to play me like they are about the truth.  They're about gaining sales,
bringing in the customer revenues, and grabbing market share; not truth.

Now if your users want to step up & write an honest warts-and-all hands-on
review of your test tools (that realistically covered your True-Time ATPG's
real life flaws & strengths) -- THEN and only then I'd believe your "proofs".

And besides, Tom, what percentage of the Scan/ATPG market does Cadence have?
Something like 2%?  This is a Synopsys vs. Mentor battle; Cadence is only a
wannabe poser here.  Cadence kicks ass in floorplanning, custom layout, and
emulation.  There's no question there.  Cadence owns those niches.  But it's
the Peewee Herman of the test world.  Nice try, but it ain't happening!  :)

    - John Cooley
      DeepChip.com                               Holliston, MA