After reading some benign, very forgettable story that somehow involved last
week's International Test Conference (ITC), a voice came to me.  (It wasn't
one of those John-Sure-Is-Crazy voices.  No, not this time.  Those voices
stopped telling me what to do a long time ago; after my meds had *finally*
kicked in...)  This was a little voice in my head reminding me that I should
call shenanigans on that bullshit story Synopsys Marketing tried to pass off
on us in September.

I first saw the story in EEtimes.com.  It was almost a word-for-word rehash
of the official Synopsys press release.  From the release:

  "This is the 2nd major performance enhancement Synopsys has engineered
   for TetraMAX in the span of a year," said Graham Etchells of Synopsys
   test marketing.  "Taken together, the 2 most recent TetraMAX versions
   have achieved on average more than a 12x speed-up in ATPG results."

So what am I missing here?  Is this some sort of Synopsys Marketing contrived
"study" rigged to show the world that (obviously) 4 out of 5 choosy mothers
choose Jif?  Or are the everyday users actually seeing real life benchmarks
where TetraMAX is now a kickass 12X faster?  Inquiring minds want to know!  

What type of stuck-at coverage are you seeing at these 12X faster speeds?
Are we talking about getting 80% is now 12X faster, but getting a barely
usable realistic 95% coverage is still pig slow?  What about 98%?  99%?

Also, what happens when it can't reach 100% coverage?  Really loooooooong
runtimes?  Or is TetraMAX smart enough to quickly know which faults are
reachable and which are not?

Are there ideal requirements I'm missing here?  Does this 12X claim apply
to real world designs with multiple clocks?  What about non-harmonic or
asynch clocks?  How about multi-cycle paths and false paths?  What about
tri-state busses?  What about at-speed testing?  What about LSSD designs?
What fault models is this 12X good for and not good for?  Only stuck-at's?

And, of course, is this an apples-to-apples 12X speed-up running on the same
machines on the same designs with the same memory capacity & system loads?

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I'm not naive.  I'm not expecting this 12X to apply in all corner cases.
That's unrealistic.  I'm just curious where it does and does not apply.
If this 12X holds for most real life designs, it's a serious achievement.

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The Synopsys Marketing press release went on to claim:

    "Unlike competing tools, the TetraMAX solution does not require
     partitioning of a large SoC to run ATPG separately on each block;
     instead it can generate patterns for the entire design at once."

So as a hands-on TetraMAX user, are you seeing Mentor FastScan choke on your
big ass chips?  Is FastScan pitifully crying like a baby for partitioning
(like what Synopsys Marketing implies in this press release) while TetraMAX
gleefully breezes through your chip like hot knife through butter?

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Overall, is FastScan really that broken while TetraMAX is that advanced?

Should I call shenanigans on these Synopsys marketing claims?  Or not?