!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / The 2007 DeepChip Verification Census (Part 1 & 2)
_] [_ -or-
A Census of 818 Engineers on Design Verification Tool Use
by John Cooley
( DVcon 07 Subjects ) -------------------------------------------- [ 04/24/07 ]
Part I
Item 1: Mindshare vs. Marketshare
Item 2: Verilog vs. VHDL
Item 3: Cadence NC-Sim, Synopsys VCS, Mentor ModelSim, Aldec
Item 4: Atrenta Spyglass, Synopsys Leda, Cadence HAL, 0-In CheckList
Item 5: Certess Certitude
Item 6: Nusym "DeNibulator"
Item 7: Novas Debussy & Verdi, Veritools UnderTow, DAI SignalScan
Item 8: Cadence Verisity Specman "e" vs. Synopsys Vera
Item 9: SystemC SCV and JEDA
Part II
Item 10: Mike Fister doubts this is statistically relevant
Item 11: SystemC
Item 12: System Verilog
Item 13: IEEE PSL, System Verilog SVA, Verplex OVL/IAL, 0-In CheckerWare
Item 14: Jasper, Synopsys Magellan, Mentor 0-In, Cadence IFV, IBM RuleBase
Item 15: Magellan, 0-In, IFV/BlackTie, Jasper, RuleBase, Verix, Solidify
( DVcon 07 Jobs Section ) ---------------------------------------- [ 04/24/07 ]
Job 1: West Coast, USA - EVE looking to hire numerous apps engineers
Job 2: Los Gatos, CA - start-up Nusym seeks a senior apps engineer
Job 3: Mountain View, CA - Jasper DA is looking to recruit a new CAE
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG,
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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