!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / DVcon'04 Trip Report:
_] [_ -or-
A Census of 137 Engineers on Design Verification Tool Use
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
"We don't use bug-hunters. We ARE the bug-hunters."
- John Ford of SolarFlare Communications
( DVcon 04 Subjects ) -------------------------------------------- [ 05/26/04 ]
Item 1: the Bigwig's Big Speech
Item 2: Modelsim, VCS, NC-SIM, Aldec, Icarus, SynaptiCAD, Wellspring
Item 3: SystemC
Item 4: System Verilog
Item 5: Verisity Specman "e", Synopsys Vera, SystemC SCV, JEDA
Item 6: IBM Sugar/PSL, 0-in Checkerware, Verplex OVL, System Verilog SVA
Item 7: TransEDA, Atrenta Spyglass, Novas Debussy, Verisity SureCov
Item 8: Summit Visual Elite, Mentor HDL Designer (Renoir)
Item 9: Cadence Verplex, Synopsys Formality, Mentor FormalPro, Prover eCheck
Item 10: 0-in, Jasper, Synopsys Magellan, RealIntent Verix, Averant, @HDL
Item 11: Cadence Palladium, Verisity Axis, Mentor IKOS & Celaro, EVE, Tharas
Item 12: Mentor Seamless, CoWare ConvergenSC, Annapolis CoreFire, Summit VCPU
Item 13: Synopsys DW AMBA, Denali PCI Express, Verisity USB
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG,
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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