!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / DAC'03 Trip Report:
_] [_ The We're-Back-In-California DAC in Anaheim
- or -
492 Engineers Review 2003's Crop of EDA Tools of June 2-6, 2003
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
"I was gambling in Havana. I took a little risk.
Send lawyers, guns and money. Dad, get me out of this."
- Warren Zevon, 1978
( DAC 03 Subjects ) --------------------------------------------- [ 01/20/04 ]
Item 1: the DAC numbers
Item 2: Synchronicity, Cliosoft, Perforce, Interweave
Item 3: RunTime Flowtracer
Item 4: SystemC, Mathworks, Mentor Seamless & PrecisionC
Item 5: Cadence Incisive & TestBuilder
Item 6: Forte Cynthesizer
Item 7: Summit Visual Elite, Mentor HDL Designer (Renoir)
Item 8: CoWare, LisaTek, Target Compiler, Prosilog, VaST, Y Explorations
Item 9: Celoxica DK Handel-C
Item 10: Verisity Specman "e" vs. Synopsys Vera vs. System Verilog
Item 11: 0-in, Jasper, Real Intent
Item 12: @HDL, Synopsys Magellan (Ketchum)
Item 13: Avery, Innologic, Averant, Safelogic, Synapticad, Obsidian, Jeda
Item 14: Verisity SureCov, TransEDA, VeriEZ, Synopsys Leda & CoverMeter
Item 15: Atrenta SpyGlass
Item 16: Fishtail Focus
Item 17: Novas DeBussy & nSchema & Verdi, Veritools Undertow
Item 18: Axis, Tharas, Quickturn, Pittsburgh, EVE, Aptix, Hardi, Dini Group
Item 19: Cadence Verplex, Synopsys Formality, Mentor FormalPro, Prover
Item 20: Mentor FastScan, LogicVision, TetraMAX, Syntest, Genesys, iRoC
Item 21: Synplicity Synplify & Identify & Certify
Item 22: Hier Design vs. Synplicity Amplify
Item 23: ViASIC, Synplicity Structured ASIC
Item 24: Synopsys
Item 25: Cadence First Encounter, NanoRoute, CeltIC, Simplex, Get2chip
Item 26: Magma Blast Fusion/Plan/Rail/Create
Item 27: Monterey Sonar & Dolphin & Calypso & IC Wizard
Item 28: Icinergy SoCarchitect
Item 29: Tera Systems TeraForm, InTime Time Builder
Item 30: Sequence Physical Studio, Golden Gate, Synplicity Iota, ChipVision
Item 31: Apache RedHawk-SDL & NSPICE
Item 32: Nassda HSIM & Hanex & Critic
Item 33: Cadence Virtuoso, Pulsic, Paragon, Mentor IC Station
Item 34: Silicon Canvas Laker
Item 35: Tanner L-Edit & T-Spice, Silvaco SmartSpice
Item 36: StabieSoft Slam-Edit & Strategy
Item 37: Manhattan Routing, Inc.
Item 38: Mentor Calibre & Calibre-XRC & Eldo
Item 39: NeoLinear, Antrim, Ciranova, Barcelona, ADA, Xpedion
Item 40: Sagantec, RubiCAD, Bindkey, In2Fab, Q Design
Item 41: Silicon Metrics, Prolific, Z Circuit, Zenasis, UbiTech
Item 42: Pinebush Hyperplot
Item 43: the Best & Worst DAC Parties & Giveaways
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 17,088 other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG,
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
|
|
