!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / DAC'01 Trip Report:
_] [_ "The Fear And Loathing In Las Vegas DAC"
- or -
"182 Engineers Review 2001's Crop Of EDA Tools On June 18-22, 2001"
by John Cooley
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
"Men occasionally stumble over the truth, but most of them pick themselves
up and hurry off as if nothing ever happened."
- Sir Winston Churchill, English statesman, (1874 - 1965)
( DAC 01 Subjects ) -------------------------------------------- [ 7/31/01 ]
Item 1: The DAC Numbers
Item 2: Syncronicity, Runtime, GoalSmith, Platform, Beach, Translogic
Item 3: Atrenta SpyGlass, SureLint, TransEDA, VeriLint, Veritools, Leda
Item 4: Tera System's TeraForm
Item 5: InTime, Icinergy
Item 6: Iota, Sequence/Sente WattWatcher, Synopsys Power Compiler, Offis
Item 7: The Chip Designer's Intense Hatred Of C/C++ HW Design
Item 8: Forte/CynApps, C-Level, CoWare, SystemC, Frontier, Y Explorations
Item 9: Cadence Testbuilder/Cockpits, Celoxica, Avery, FTL, Denali, Provis
Item 10: Mentor 'Platform Express', Seamless, Synopsys Eagle-i, Summit VCPU
Item 11: Foresight, Vast, Coverify, TOPS, Cynergy, Cardtools, Axys, Beach
Item 12: Debussy, @HDL, Veritools, EDAptive, iMODL, Diagonal
Item 13: Cadence NC-Verilog, Synopsys VCS, Model Tech, Synopsys Scirocco
Item 14: Verisity Specman 'e', Synopsys Vera, Forte/Chronology RAVE
Item 15: Superlog, Verilog-2000
Item 16: Verplex, Formality, Chrysalis, Cadence 'Formal Check'
Item 17: The Intel Case Study & Harry Foster's Assertion Checkers Hell
Item 18: 0-in, Synopsys 'Ketchum'
Item 19: Real Intent 'Verix'
Item 20: GreenLight, SynaptiCAD
Item 21: Averant 'Solidify', @HDL, Prover
Item 22: Quickturn, IKOS, Aptix, Axis, Simpod, Tharas, Simutech, Gidel
Item 23: TetraMax, Fastscan, LogicVision, SynTest, Intellitech, Fluence
Item 24: Exemplar vs. Synplicity vs. Synopsys FPGA Express
Item 25: Design Compiler, Ambit-RTL, Get2chips.com, Synplicity, Incentia
Item 26: Quickie Intro To Backend Tools For Frontend Designers
Item 27: Synopsys PhysOpt vs. Cadence PKS
Item 28: Magma 'BlastFusion'
Item 29: Monterey, Sequence/Sapphire, Mentor TeraPlace, Saturn/Jupiter
Item 30: 'Hidden Dragon', Silicon Perspectives, 'Integration Ensemble'
Item 31: Plato, Avanti, Cadence 'Silicon Ensemble', Synopsys Route66, Magma
Item 32: Silicon Valley Research, InternetCAD
Item 33: Calibre, Hercules, Cadence DRC/LVS, Avanti Cosmos, K2, Assura
Item 34: Simplex & Simplex 'X Technology'
Item 35: PrimeTime-SI, Mars Xtalk, Sequence, Incentia, Ansoft, Optem
Item 36: Nassda, EPIC, Celestry, Tanner, Silvaco, Silos3, Mach TA, SPICE
Item 37: Sagantec, Rubicad
Item 38: Silicon Metrics, Cadabra, Numerical, Circuit Semantics, InnoLogic
Item 39: Artisan, Virage, Nurlogic, Library Technologies, Virtual Silicon
Item 40: NeoLinear, Antrum, Barcelona, Analog DA, ComCAD
Item 41: Cores (ASIC & FPGA), Core Tools, Core Websites
Item 42: The Best/Worst DAC Parties & Freebies
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 11,000+ other users
dealt with it? Then join the E-Mail Synopsys Users Group (ESNUG)!
!!! "It's not a BUG, jcooley@world.std.com
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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