"NextOp would have been lost inside of the Synopsys empire."
- Mike Gianfagna on why NextOp went Atrenta vs. SNPS
( ESNUG 526 Subjects ) ------------------------------------------ [06/28/13]
Item 1: Joe Costello on Oasys, Montana, EDA, Design Compiler, estimation
Item 2: Dean Drako on IC Manage, IP reuse, design mgmt, GDP, ICM Views
Item 3: Mike Gianfagna on NextOp, Synopsys, IPO, Apache, Denali, bundles
Item 4: Joe Sawicki on Calibre, 10 nm, iJTAG, Veloce 2, Olympus-SoC, PCB
Item 5: Silicon guys, Magma, Hogan's alimony, Cadence IP, C, Big 3, Icahn
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Read what 33,018 engineers REALLY think of the EDA/IP/FAB tools they use!
!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
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