"I heard from a colleague just returning from Taiwan that TSMC is
moving to a 4 day week schedule (not to four 10 hour days, but
to four 8 hour days). TSMC employees can use their vacation time
for the fifth day, or go without pay."
- [ An Anon Engineer ]
( ESNUG 478 Subjects ) ------------------------------------------ [12/18/08]
Item 1: With Gary Smith warning, what should replace SoC Encounter?
Item 2: Cadence has tweaked RTL Compiler Physical for better P&R results
Item 3: A user-written tutorial on how to use IC Manage on your projects
Item 4: Breker CEO explains his graph-based "intelligent testbench" tool
Item 5: Is Knowlent dead? How about Blaze DFM? How about Stone Pillar?
Item 6: Oops! Synopsys Support web site uses Cadence Virtuoso graphics!
Item 7: Virage bails on its unwanted $10 million takeover of LogicVision
Item 8: ( ESNUG 477 #3 ) Power Opto and Linting in CatapultC and Spyglass
Item 9: ( ESNUG 477 #3 ) Using Calypto SLEC in a CatapultC design flow
Item 10: ( ESNUG 477 #4 ) Synopsys SolvNet's insane new password rules
============================================================================
Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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