"The company expects to eliminate at least 625 full-time positions,
representing 12% of its global employee base, plus a substantial
number of contractors and consultants."
- Cadence press release 11/05/08
( ESNUG 477 Subjects ) ------------------------------------------ [11/20/08]
Item 1: Cadence Connections evicts 48 companies 3 days before deadline
Item 2: 7 users benchmark PrimeTime 2007.12 versus PrimeTime 2007.06
Item 3: ( ESNUG 476 #9 ) The first US-based C/C++ chip design I've seen
Item 4: The overly paranoid Synopsys Solvnet's insane new password rules
Item 5: We switched from Hercules to Calibre for Equation-based DRCs
Item 6: Why we dumped PrimeTime (and skipped Cadence ETS) for GoldTime
Item 7: ( ESNUG 476 #1 ) User questions if Sierra MCMM is tipping point
Item 8: ( ESNUG 476 #6 ) Hold on! Our Apache experience was quite bad
Item 9: ( ESNUG 475 #10 ) Uh, actually Synopsys supports both UPF flows
Item 10: ( ESNUG 475 #10 ) Bluespec is the "biggest lie in ESL space"
( ESNUG 477 White Papers ) -------------------------------------- [11/20/08]
Vid 1: Video -- IC Manage's Design Management Tutorial Videos
WP 2: RTL for Power with Sequence PowerArtist and PowerTheater
These items are at http://www.deepchip.com/whitepapers.html
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Trying to figure out a Synopsys bug? Want to hear how 24,298 other users
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!!! "It's not a BUG, 
/o o\ / it's a FEATURE!" (508) 429-4357
( > )
\ - / - John Cooley, EDA & ASIC Design Consultant in Synopsys,
_] [_ Verilog, VHDL and numerous Design Methodologies.
Holliston Poor Farm, P.O. Box 6222, Holliston, MA 01746-6222
Legal Disclaimer: "As always, anything said here is only opinion."
The complete, searchable ESNUG Archive Site is at http://www.DeepChip.com
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